Dynamic semiconductor multi-value memory device

Details Dynamic semiconductor multi-value memory device Dynamic semiconductor multi-value memory device

1991-07-05

1993-02-02

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Capacitors

365203, G11C 510

Patent

active

051843242

ABSTRACT:
A dynamic semiconductor multi-value memory device has memory cells each of which includes a series circuit of one storage capacitor and two transistors. A first capacitor is connected between a first bit line of a first bit line pair and a second bit line of a second bit line pair which is adjacent to the first bit line pair. A second capacitor is connected between a second bit line of the first bit line pair and a first bit line of the second bit line pair.

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A. Tanabe et al., Autumn National Convention of Electronic Information Communication Society, "Boost Sense Amplifier for Low Voltage Operation DRAM" 1990, p. 5-256.
Y. Ohta et al., Sharp Gihoh, vol. 44, pp. 47-50, Mar. 1990, "A Novel Memory Cell Architecture for High-Density DRAMS" with partial English Translation.

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