Dynamic semiconductor memory with refresh function

Static information storage and retrieval – Read/write circuit – Data refresh

Patent

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Details

3652257, 365191, 365193, G11C 700

Patent

active

053294904

ABSTRACT:
The memory cell array in accordance with the invention is divided into several memory cell array portions, each memory cell array portion having refresh period determined so as to be adapted to a memory cell having minimum data retention time among memory cells therein. The invention can greatly reduce consumption of electrical power by refresh relative to the conventional memory cell array.

REFERENCES:
patent: 4829484 (1989-05-01), Arimoto
patent: 4934826 (1990-06-01), Miyatake
patent: 4951258 (1990-08-01), Uehara

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