Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-03-28
2003-07-08
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S230060
Reexamination Certificate
active
06590824
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of integrated circuits. The invention relates to a semiconductor memory having at least one memory bank including dynamic memory cells. The memory cells are disposed in rows and are addressable through a word line. When a memory cell is accessed, the respective word line is activated. A control device provides for a refresh operation. The invention additionally relates to a method for operating such a semiconductor memory.
Dynamic semiconductor memories contain memory cells that conventionally include a selection transistor and also a storage capacitor. The memory cells are disposed in a plurality of memory banks. A memory bank contains all the functional units for performing an access to a memory cell. The memory banks can be operated independently of one another. Within a memory bank, the memory cells are disposed in rows. All the memory cells of a row are addressable by a word line. When the word line is activated, the selection transistors of the memory cell are turned on so that the storage capacitor is respectively connected to a bit line. The stored data value is available on the bit line ready for read-out after amplification by a sense amplifier.
Unavoidable leakage currents in the semiconductor chip reduce the quantity of charge that is stored in the storage capacitor and represents either a logic “1” or a logic “0”. The charge content of the memory cell must, therefore, be refreshed from time to time. The refresh interval is typically 64 milliseconds. During the refresh operation, for all the word lines and the memory cells of a memory bank that are connected thereto, in each case after the activation of the word line, the data content of the memory cells is amplified in the sense amplifier. Afterward, the amplified level is written back to the memory cell. Finally, the word line is deactivated, so that the selection transistors of the memory cells connected thereto are turned off.
In system applications with dynamic semiconductor memories, for example, in the case of personal computers, a memory controller is provided as a separate semiconductor chip to control the accesses to the dynamic semiconductor memory. Conventional memory controllers store the address of the respectively open row for one of the open memory banks of an addressed semiconductor memory. Because, during the processing of programs or data stored in the semiconductor memory, it can be assumed with high probability that subsequent memory accesses are made to successive memory addresses and, hence, adjacent memory cells, it is possible, due to the buffer-storage of the address of the already activated row of a memory bank, in principle, to accelerate the access to the memory bank.
In today's system applications, however, endeavors are made to the effect that, in the event of a read access to the semiconductor memory, usually relatively large data blocks are read out and buffer-stored in a fast buffer memory, a so-called cache memory. By way of example, a sufficiently short loop of an operating program is loaded completely from the dynamic semiconductor memory into the cache memory, which is significantly faster by comparison, and is multiply iterated. Even if the subsequent access to the dynamic semiconductor memory is effected compared with a preceding access to adjacent memory cells that are spatially close together, so much time has already elapsed through the processing of the program loop of the main memory that a refresh operation has been necessary in the meantime. Because all the word lines are run through during the refresh operation, without further measures, the information about the activated word line that was previously ready for access is no longer present on the semiconductor memory. If the memory controller has stored the address of the previously activated word line, the address must be retransmitted to the semiconductor memory to reactivate there the row that was activated before the refresh operation. Such is true because, in accordance with the specification for synchronously operating dynamic semiconductor memories, so-called SDRAMs, before a refresh command can be applied to the SDRAM, all the memory banks must be put into the precharged state, the so-called precharge all state, so that all the word lines are deactivated and set to reference-ground potential. Only if the memory controller has corresponding registers in which the address of the activated row has been buffer-stored and transmits the address with a corresponding activate command after a refresh operation for the relevant memory bank to the dynamic semiconductor memory is such a memory bank, and, therein, the relevant row or word line, then activated. On one hand, the process has the disadvantage that the access speed is reduced because, on the semiconductor memory itself, the information about the open row is lost due to the refresh operation and the information has to be retransmitted from the memory controller after the refresh operation. On the other hand, additional data traffic is generated that burdens the memory bus in the system and, therefore, also impairs the operating speed.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a dynamic semiconductor memory with refresh that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that improves a dynamic semiconductor memory of the type mentioned in the introduction to the effect memory accesses faster, in particular, the intention is that a refresh operation will not impair the access readiness of the dynamic semiconductor memory more than necessary.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory including at least one memory bank having dynamic memory cells disposed in rows and word lines, the memory cells of one of the rows being connected to and addressed by one of the word lines, the one word line being activated for access of one of the memory cells connected to the one word line, a memory element connected to the memory bank and storing an address associated with an activated one of the word lines, and a control device connected to the memory bank, the control device programmed to refresh the memory bank by resetting all of the word lines of the memory bank and to activate one of the word lines having the address stored in the memory element after refreshing the memory bank.
With the objects of the invention in view, there is also provided a method for operating a semiconductor memory including the steps of providing at least one memory bank having dynamic memory cells disposed in rows, addressing the memory cells of a row through a word line and accessing a memory cell by activating the word line connected to the memory cell, storing an address of an activated word line of the memory bank, refreshing the charge content of all the memory cells of the memory bank, and after the refresh, activating again the word line within the memory bank associated with the stored address.
In accordance with another mode of the invention, a first state of an identifier associated with the memory bank is stored if a word line has been activated in the memory bank and a second state of the identifier is stored if no word line is activated in the memory bank, and after the refresh, the word line associated with the stored address is activated and the identifier is set from the second state to the first state.
In the case of the dynamic semiconductor memory according to the invention, a memory element, expediently a register, is provided on the semiconductor memory itself, in a manner associated with each memory bank to buffer-store that address assigned to the currently activated word line. In principle, it suffices if the address of the activated memory cell is buffer-stored only before a refresh operation. Previously, such information was, at most, buffer-stored in the memory controller. During the refresh, the c
Barth Roland
Benedix Alexander
Düregger Reinhard
Hermann Robert
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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