Dynamic semiconductor memory with improved sensing scheme

Static information storage and retrieval – Read/write circuit – Data refresh

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Details

365189, 365207, 365210, G11C 700, G11C 1140

Patent

active

048113026

ABSTRACT:
An improved dynamic memory device having a high-speed operation and an increased utilization ratio is disclosed. The memory comprises first and second pairs of digit lines and first and second sense amplifiers and is featured in that the first and second sense amplifiers are electrically connected in parallel and commonly used to amplify a signal difference between a selected one pair of the first and second digit lines with the other non-selected pair of digit lines electrically isolated from the both sense amplifiers in an access mode, and the first and second sense amplifiers are independently connected to the first digit lines and second digit lines, respectively in a refresh mode.

REFERENCES:
patent: 4207618 (1980-06-01), White, Jr. et al.
patent: 4739500 (1988-04-01), Miyamoto et al.

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