Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2010-11-05
2011-12-06
Phung, Andy (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030
Reexamination Certificate
active
08072829
ABSTRACT:
Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at the same time as normal access for read/write operation. In a specific embodiment, to resolve conflicts between addresses, an address comparator compares the address for normal access to the address for refresh operation. In case of a match between the two addresses, the invention cancels the refresh operation at that array and allows the normal access to proceed.
REFERENCES:
patent: 4322825 (1982-03-01), Nagami
patent: 5835401 (1998-11-01), Green et al.
patent: 6005818 (1999-12-01), Ferrant
patent: 6154409 (2000-11-01), Huang et al.
patent: 6195303 (2001-02-01), Zheng
patent: 6240045 (2001-05-01), Haraguchi et al.
patent: 6282606 (2001-08-01), Holland
patent: 6366515 (2002-04-01), Hidaka
patent: 6438016 (2002-08-01), Keeth et al.
patent: 6445636 (2002-09-01), Keeth et al.
patent: 6449204 (2002-09-01), Arimoto et al.
patent: 6529433 (2003-03-01), Choi
patent: 6584028 (2003-06-01), Kyung
patent: 6757200 (2004-06-01), Keeth et al.
patent: 6813211 (2004-11-01), Takatsuka et al.
patent: 6859407 (2005-02-01), Suh
patent: 6859415 (2005-02-01), Takatsuka et al.
patent: 6862238 (2005-03-01), Lee
patent: 6871261 (2005-03-01), Proebsting
patent: 6941415 (2005-09-01), Ryan
patent: 7042785 (2006-05-01), Kim
patent: 7088632 (2006-08-01), Pelley
patent: 7313047 (2007-12-01), Kim
patent: 2001/0008496 (2001-07-01), Leung
patent: 2003/0218930 (2003-11-01), Lehmann et al.
patent: 2004/0032772 (2004-02-01), Takahashi
patent: 2008/0137464 (2008-06-01), Kim
patent: 1471710 (2004-01-01), None
patent: 1620649 (2005-05-01), None
patent: 61-269296 (1986-11-01), None
patent: 05-347093 (1993-12-01), None
patent: 08-129881 (1996-05-01), None
patent: 11-505056 (1999-05-01), None
patent: 11-250657 (1999-09-01), None
patent: 11-312386 (1999-11-01), None
patent: 11-339469 (1999-12-01), None
patent: 2000-251467 (2000-09-01), None
patent: 2002-133865 (2002-05-01), None
patent: 2002-304885 (2002-10-01), None
patent: 2002-358779 (2002-12-01), None
patent: 10-2003-0071783 (2003-09-01), None
patent: 10-2003-0088026 (2003-11-01), None
patent: 501134 (2002-09-01), None
patent: 571312 (2004-01-01), None
patent: WO 97/30453 (1997-08-01), None
patent: WO 0215194 (2002-02-01), None
patent: WO 2005/119687 (2005-12-01), None
Chinese Office Action for Application No. 200610105992.X, dated Nov. 7, 2008, 9 pages.
Haeggqwist; “A dynamic memory with simple controls. Hidden refresh for processors”; Elektronik, 1983, pp. 45-46, with 1 page English language abstract, vol. 32, No. 26.
Huang, et al.; “A Low-Voltage Loadless 4N SRAM with Smart Hidden Refresh”; Department of Electronic Engineering Fu-Jen Catholic University, Taiwan, 2003, pp. 251-252.
Miyamoto, et al.; “Improved Address Buffers, TTL Input Current Reduction, and Hidden Refresh Test Mode in a 4-Mb DRAM”; IEEE Journal of Solid State Circuits, 1990, pp. 525-530, vol. 25, No. 2.
Sawada, et al.; “A 30-μ A Data-Retention Pseudostatic RAM with Virtually Statis RAM Mode”; IEEE Journal of Solid-State Circuits, 1998, pp. 12-19, vol. 23, No. 1.
“The 80C186XL/80C188XL Integrated Refresh Control Unit,” Intel, (undated) 15 pages.
“Toshiba 1 Mb DRAM sees Silicon”; Integrated Circuits International, 1984, pp. 11-14, vol. 8, No. 9.
Notice of Allowance for U.S. Appl. No. 11/378,183, mailed on Aug. 27, 2007, 9 pages.
Supplemental Notice of Allowance for U.S. Appl. No. 11/378,183, mailed on Oct. 11, 2007, 6 pages.
Requirement for Restriction/Election for U.S. Appl. No. 11/985,580, mailed on Mar. 22, 2010, 5 pages.
Notice of Allowance for U.S. Appl. No. 11/985,580, mailed on Jul. 22, 2010, 18 pages.
Hynix / Semiconductor Inc.
Kilpatrick Townsend & Stockton LLP
Phung Andy
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