Dynamic semiconductor memory with improved refresh mechanism

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S233100

Reexamination Certificate

active

11378183

ABSTRACT:
Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at the same time as normal access for read/write operation. In a specific embodiment, to resolve conflicts between addresses, an address comparator compares the address for normal access to the address for refresh operation. In case of a match between the two addresses, the invention cancels the refresh operation at that array and allows the normal access to proceed.

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Sawada, Kazuhiro et al.; “A 30-μ A Data-Retention Pseudostatic RAM with Virtually Statis RAM Mode”; 1998, IEEEJournal of Solid-State Circuits, vol. 23, No. 1, pp. 12-19.
“The 80C186XL/80C188XL Integrated Refresh Control Unit”, 15 pages.

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