Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-06-12
2009-12-08
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S236000
Reexamination Certificate
active
07630268
ABSTRACT:
A dynamic semiconductor memory has a plurality of memory blocks and a memory core. Each of the memory blocks has a sense amplifier, and the memory core is formed from memory cells located at intersections between a plurality of word lines and a plurality of bit lines connected to the sense amplifier. The memory blocks are sequentially refreshed by selecting each of the word lines and by simultaneously activating the memory cells connected to the selected word line by the sense amplifier. The dynamic semiconductor memory has a first refresh counter which outputs a first internal refresh candidate address, and a second refresh counter which outputs a second internal refresh candidate address that is different from the first internal refresh candidate address. When an externally accessed address coincides with the first internal refresh candidate address, a refresh operation is performed starting from the second internal refresh candidate address.
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Taiwanese Office Action dated Dec. 10, 2009 for a related Taiwanese application.
Fujitsu Microelectronics Limited
Fujitsu Patent Center
Hoang Huan
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