Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Patent
1993-03-09
1994-07-26
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
365204, 36518901, G11C 700
Patent
active
053331214
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a dynamic semiconductor memory.
A dynamic semiconductor memory of this type is known from the publication entitled "An Experimental 16 Megabit DRAM with Reduced Peak-Current Noise" by B. Chin (Samsung) from the Digest of Technical Papers from the 1989 Symposium on VLSI Circuits (pages 113 and 114). This relates to a dynamic semiconductor memory having lines which are interconnected in a block manner to metal conductors lying above ( metal strapping ) in order to reduce the line resistance, and which has distributed SAN and SAP drivers, consisting of a transistor, in each case one SAN driver transistor and one SAP driver transistor being present for each read amplifier. Since two additional transistors are thus required for each read amplifier, this entails a relatively high additional space requirement.
SUMMARY OF THE INVENTION
The object of the invention is to disclose a dynamic semiconductor memory of the type mentioned at the beginning which permits an optimum combination of evaluation reliability and short access time with a minimum chip space requirement. This object is achieved according to the invention by a dynamic semiconductor memory having a memory cell arrangement which has at least one word line block. Read amplifiers have in each case an n-channel part and a p-channel part. At least one SAN driver per word line block drives the n-channel parts of the read amplifiers and at least one SAP driver per word line block drives the p-channel parts of the read amplifiers. At least one word line block has a multiplicity of bit line blocks. The bit line blocks in turn have a multiplicity of bit line pairs, wherein, to the extent that word lines are made contact with through the board, the word lines having superimposed conductor tracks which are of low impedance relative to the word lines and which have word line pins, the bit line pairs located in each case between two word line pins of a word line form a bit line block. To the extent that word lines are guided only in a plane of low-impedance material and additional word line drives are provided, the bit line pairs located in each case between two word line drivers of a word line form a bit line block. Wherein a single SAN driver is present for each bit line block, forms a local SAN driver and can be driven such that the voltage at its output decreases in a piecemeal manner, with different gradients, to enable a fast and at the same time reliable reading. Wherein in each case one local SAN driver drives the n-channel parts of all read amplifiers belonging to a bit line block via a local SAN line.
The particular advantage conferred by the invention is that, with the dynamic semiconductor memory designed according to the invention, in comparison with the cited dynamic semiconductor memory from Samsung, no additional space is required by virtue of an n-phase driver which is required only on a block basis with optimized drive function and, for example, the utilization of a gap between read amplifier blocks already formed by through-plated line interconnects.
Further developments of the present invention are as follows.
The local SAN driver belonging to a bit line block is arranged spatially on a semiconductor chip in such a way that it is located between an arrangement of read amplifiers belonging to the bit line block and an arrangement of read amplifiers which belong to the bit line block directly adjacent to the bit line block.
In each case one local SAN driver contains a diode, which is connected to a reference potential on the cathode side and is connected to a first terminal of a first n-channel transistor on the anode side. A second terminal of the first n-channel transistor is connected to a driver output of the local SAN driver and the gate terminal of the first n-channel transistor can be driven by a first control signal. A second n-channel transistor is connected in parallel with the diode and its gate can be driven by a second control signal. A first terminal of a third n-channel transis
REFERENCES:
patent: 4050061 (1977-09-01), Kitagawa
patent: 4543501 (1985-09-01), McAlexander, III et al.
patent: 4694205 (1987-09-01), Shu et al.
patent: 4796234 (1989-01-01), Itoh et al.
patent: 4943949 (1990-07-01), Yamaguchi et al.
patent: 5222038 (1993-06-01), Tsuchida et al.
"Column Address Controlled Sense Amplifier Latching Circuit for DRAM" IBM Technical Disclosure bulletin, vol. 32, No. 2, Jul. 1989, pp. 277-280.
"A 65ns CMOS DRAM with a Twisted Driveline Sense Amplifier" by Shimohigashi et al, IEEE International Solid State Circuits Conference, Feb. 25, 1987, New York, pp. 18, 19, 318, 319.
"Decoded-Source Sense Amplifier for High-Density DRAM's", by Okamura et al, IEEE Journal of Solid-State Circuits, Feb. 25, 1990, No. 1, New York, pp. 18-22.
"An Experimental 16Mb DRAM with Reduced Peak-Current Noise" by Chin et al, 1989 Symposium on VLSI Circuits Digest of Technical Papers, pp. 113-114.
LaRoche Eugene R.
Le Vu
Siemens Aktiengesellschaft
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