Dynamic semiconductor memory device with SOI structure and body

Details Dynamic semiconductor memory device with SOI structure and body Dynamic semiconductor memory device with SOI structure and body

1997-04-14

1998-10-13

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, 36518909, G11C 700

Patent

active

058222642

ABSTRACT:
A semiconductor memory device of a silicon-on-insulator (SOI) structure is provided that can have majority carriers stored in a body region discharged without increasing a memory cell area. A body refresh circuit adjusts a row related control signal from a local row related control circuit and a bit line precharge voltage according to body refresh designating signals. When body refresh is specified and is to be carried out in parallel to CBR refresh, a column select line is driven to a selected state according to an output signal of a shift register. Low level data from a write circuit is transmitted to each bit line in a selected bit line pair. In a self refresh operation, a bit line precharge voltage applied to a bit line equalize circuit group is reduced to the voltage of an Low level.

REFERENCES:
patent: 5418754 (1995-05-01), Sakakibara
patent: 5654913 (1997-08-01), Fukushima et al.
1996 Symposium on VLSI Circuits, Jun. 13-15, 1996/Honolulu pp. 189-200.

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