Dynamic semiconductor memory device with reduced current...

Details Dynamic semiconductor memory device with reduced current... Dynamic semiconductor memory device with reduced current...

1999-12-07

2002-01-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S205000

Reexamination Certificate

active

06337824

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a dynamic semiconductor memory device having a sense amplifier differentially amplifying memory cell data. More specifically, the present invention relates to the structure of a drive part for the sense amplifier.
2. Description of the Background Art
Following the recent development and spread of computers and information processing terminals, requirement for devices employed as main storage in these equipments is increasingly severe. With respect to a DRAM (dynamic random access memory) most widely utilized as the main storage, a DRAM capable of transferring data at a high speed such as an SDRAM (synchronous DRAM) inputting/outputting data in synchronization with a clock signal or a DDR (double data rate) SDRAM inputting/outputting data in synchronization with both leading and trailing edges of a clock signal is now in the process of popularization.
The DRAM stores information in a capacitor of a memory cell in the form of charges. High-level data written in a DRAM cell is spontaneously disappears due to a leakage current when left intact, and must be periodically restored through an operation referred to as refresh.
The specification for a recent DRAM defines an operation referred to as self-refresh. In such a self-refresh operation mode, a timer in the DRAM automatically sets a refresh timing for automatically performing the refresh operation.
The self-refresh operation is performed in a standby state when no access is made to DRAM. Therefore, a continuous wait time in a portable communication information terminal, for example, can be increased by suppressing a self-refresh current consumed in the self-refresh operation (since the life time of a battery can be prolonged).
Among components of the self-refresh current, what accounts for the largest percentage is a current for reading data stored in a memory cell and rewriting the data, i.e., the so-called sense current Issr. This sense current is now described.
FIG. 27
illustrates the structure of a memory cell array of a conventional DRAM. Referring to
FIG. 27
, the DRAM includes memory cells MC arranged in a matrix of rows and columns, a pair of bit lines BL and /BL arranged in correspondence to each column of the memory cells and a word line WL arranged in correspondence to each row of the memory cells MC.
FIG. 27
representatively shows a single memory cell MC. Memory cell MC includes a memory cell capacitor Cs for storing information and an access transistor MT formed by an n-channel MOS transistor and rendered conductive in response to the signal voltage on word line WL for connecting the memory cell capacitor Cs with bit line BL. Bit lines BL and /BL have parasitic capacitances Cb respectively.
A bit line equalize/precharge circuit E/P precharging and equalizing the bit lines BL and /BL to an intermediate voltage Vble in response to a bit line equalization instruction signal BLEQ and a sense amplifier circuit S/A differentially amplifying the voltages of bit lines BL and /BL in response to sense amplifier activation signals SON and ZSOP are provided for bit lines BL and /BL.
Bit line equalize/precharge circuit E/P includes precharge transistors Q
7
and Q
8
transmitting the intermediate voltage Vble to bit lines BL and /BL respectively in response to bit line equalization instruction signal BLEQ and an equalize transistor Q
9
shorting the bit lines BL and /BL in response to bit line equalization instruction signal BLEQ. The transistors Q
7
to Q
9
are formed by n-channel MOS transistors (insulated gate field effect transistors).
Sense amplifier circuit S/A includes an N sense amplifier activated in activation of the sense amplifier activation signal SON for discharging one of bit lines BL and /BL at a lower potential and a P sense amplifier activated in activation of the sense amplifier activation signal ZSOP for charging one of bit lines BL and /BL at a higher potential. N sense amplifier includes an n-channel MOS transistor Q
1
having a drain connected to bit line BL and a gate connected to bit line /BL, an n-channel MOS transistor Q
2
having a drain connected to bit line /BL and a gate connected to bit line BL and an n-channel MOS transistor Q
3
rendered conductive in activation of sense amplifier activation signal SON for transmitting a sense power supply voltage Vsan to sources of the MOS transistors Q
1
and Q
2
. The sense power supply voltage Vsan is generally at the level of a ground voltage Vsg.
P sense amplifier includes a p-channel MOS transistor Q
4
having a drain connected to bit line BL and a gate connected to bit line /BL, a p-channel MOS transistor Q
5
having a drain connected to bit line /BL and a gate connected to bit line BL and a p-channel MOS transistor Q
6
rendered conductive in activation of sense amplifier activation signal ZSOP for transmitting a sense power supply voltage Vsap to sources of the MOS transistors Q
4
and Q
5
. Sense power supply voltage Vsap is generally at the level of a power supply voltage Vdds. A refresh operation for memory cell MC will be now described with reference to a signal waveform diagram shown in FIG.
28
.
In a standby state, sense amplifier activation signal SON is low at the ground voltage Vss, sense amplifier activation signal ZSOP is inactive at the power supply voltage Vdds, and sense amplifier circuit S/A is inactive. Bit line equalization instruction signal BLEQ is in a high-level active state, and all MOS transistors Q
7
to Q
9
included in bit line equalize/precharge circuit E/P are rendered conductive so that bit lines BL and /BL are precharged and equalized to the level of intermediate voltage Vble. The intermediate voltage Vble is generally at a level of half the power supply voltage Vdds (=Vdds/2). Word line WL is at the level of ground voltage Vsg, and access transistor MT of memory cell MC remains non-conductive.
When a memory cycle is started, bit line equalization instruction signal BLEQ falls to a low level, bit line equalize/precharge circuit E/P is inactivated and bit lines BL and /BL enter electrically floating states at the level of intermediate voltage Vble.
Then, a row selection circuit (not shown) drives the word line WL to a selected state in accordance with an address signal, and the voltage level of word line WL increases. When the voltage level of word line WL exceeds the gate-to-source voltage of access transistor MT by a level corresponding to the threshold voltage of the access transistor, access transistor MT starts conducting, and electric charges move between bit line BL and memory capacitor Cs. Referring to
FIG. 28
, the memory cell MC stores high-level data and the voltage level of bit line BL increases.
Bit line /BL connected with no memory cell remains at the level of intermediate voltage Vble.
When the voltage difference between bit lines BL and /BL is sufficiently enlarged, sense amplifier activation signals SON and ZSOP are activated. When sense amplifier activation signal SON is activated to go high, MOS transistor Q
3
is rendered conductive in sense amplifier circuit S/A to transmit the sense power supply voltage Vsan to the sources of MOS transistors Q
1
and Q
2
. Responsively, N sense amplifier is activated and bit line /BL at a lower potential is discharged to the level of sense power supply voltage Vsan (=Vsg). When sense amplifier activation signal ZSOP is activated to go low, MOS transistor Q
6
is rendered conductive in sense amplifier circuit S/A to transmit the sense power supply voltage Vsap to the sources of MOS transistors Q
4
and Q
5
, and P sense amplifier is activated. P sense amplifier charges the bit line BL at a higher potential to sense power supply voltage Vsap (=Vdds).
Word line WL is at the level of a voltage Vpp higher than power supply voltage Vdds. Therefore, the high-level data at the level of power supply voltage Vdds on bit line BL is transmitted to memory cell capacitor Cs with no influence by thresho

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