Dynamic semiconductor memory device with higher density bit line

Details Dynamic semiconductor memory device with higher density bit line Dynamic semiconductor memory device with higher density bit line

1995-03-13

1996-11-26

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, H01L 27108

Patent

active

055788475

ABSTRACT:
A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

REFERENCES:
patent: 4574465 (1986-03-01), Rao
patent: 5025294 (1991-06-01), Erna
patent: 5091761 (1992-02-01), Hiraiwa et al.
patent: 5095346 (1992-03-01), Bae et al.
patent: 5177575 (1993-01-01), Ikeda
patent: 5332923 (1994-07-01), Takeuchi
patent: 5442212 (1995-08-01), Eimori
IEDM Technical Digest, pp. 236-239, K. Nakamura, et al., Dec. 1984, "Buried Isolation Capacitor (BIC) Cell For Megabit Mos Dynamic Ram".
IEDM Technical Digest, pp. 596-599, S. Kimura, et al., Dec. 1988, "A New Stacked Capacitor Dram Cell Characterized By A Storage Capacitor On A Bit-Line Structure".

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