Dynamic semiconductor memory device with adjustable refresh...

Details Dynamic semiconductor memory device with adjustable refresh... Dynamic semiconductor memory device with adjustable refresh...

2002-07-11

2003-09-30

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000, C365S189070

Reexamination Certificate

active

06628560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to dynamic semiconductor memory devices. In particular, the invention relates to a structure of a dynamic semiconductor memory device having a self-refresh function with controllable timing for starting a refresh operation within a chip of the semiconductor memory device.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as DRAM) is structured with memory cells each storing information by the amount of charge accumulated on a capacitor. The charge accumulated on the capacitor is lost over time. Therefore, the lost charge should be compensated for by a periodic refreshing in the DRAM according to the information retained in the capacitor of the memory cell.
One refresh operation, namely so-called “self-refresh” operation is performed with controlled timing for starting refreshing of circuitry within a chip.
Then, a semiconductor memory device having such a self-refresh function needs a self-refresh timer for determining timing for starting refreshing. For a general DRAM, the self-refresh timer generates a pulse once per 16 &mgr;sec, for example. According to this pulse, a refresh operation is carried out.
Requirements to be satisfied by such a refresh timer are that:
1) power consumption is small enough to achieve reduction of supply current for retaining data;
2) oscillation frequency does not vary with respect to variations in supply voltage and temperature; and
3) oscillation frequency does not vary even if process parameters for example change, or post-tuning is possible.
The third requirement is particularly described in detail below.
The self-refresh timer for controlling the self-refresh operation as described above includes a transistor as its component having threshold voltage Vth, gate length and gate width for example which vary depending on process changes. A resultant problem is that the oscillation frequency itself of an oscillator of the timer could vary.
Then, in order to posteriorly adjust such variations of characteristics due to process parameters as described above, the oscillation frequency of the self-refresh timer is preferably tunable after a wafer process.
FIG. 7
is a schematic block diagram showing a structure of a conventional self-refresh timer
8000
.
Self-refresh timer
8000
includes a source oscillator
8010
constituted of an inverter chain for example, a programmable counter
8100
, and a preset holding circuit
8200
for holding a preset value used for tuning. The preset value is not limited to a specific value. For example, the preset value can be programmed after a wafer process by a fuse element, for example.
Source oscillator
8010
operates with a considerably long oscillation cycle period of several &mgr;sec for the purpose of reducing power consumption. An output frequency of this source oscillator
8010
is divided by programmable counter
8100
by an integral divisor so that pulse signal Ref.Clk is output for a self-refresh operation. The divisor used by programmable counter
8100
can posteriorly be adjusted to tune the cycle period of the output from self-refresh timer
8000
.
Specifically, programmable counter
8100
includes a flip-flop circuit
8102
having its input node D receiving an input signal composed of multiple bits, the input signal being supplied to its output node Q according to activation of the output from source oscillator
8010
, an adder
8104
receiving the output from flip-flop circuit
8102
to increment the output by one, a comparator
8110
having one input receiving the output from flip-flop circuit
8102
and the other input receiving from preset holding circuit
8200
a preset value which can externally be set and outputting a comparison result, and an AND circuit
8120
receiving the output from comparator
8110
and the output from source oscillator
8010
to output reference clock signal Ref.Clk used for a self-refresh operation. A reset command is issued, at a certain clock, to flip-flop circuit
8102
by the output from comparator
8110
, and, at the following clock, the output from flip-flop circuit
8102
is reset.
FIG. 8
is a timing chart illustrating an operation of self-refresh timer
8000
shown in FIG.
7
.
It is supposed here that the preset value is 4 for describing the operation by using FIG.
8
. Referring to
FIG. 8
, OSC represents an output from source oscillator
8010
. The number of times output OSC is activated is added by flip-flop circuit
8102
and adder
8104
. When flip-flop circuit
8102
outputs
4
, comparator
8110
has its output level of “H” level (logical high level, hereinafter H level). Accordingly, reference clock Ref.Clk is supplied from AND circuit
8120
.
At the following clock of source oscillator
8010
, the output from flip-flop circuit
8102
is reset and thus the output from comparator
8110
is also reset. Then, AND circuit
8120
has its output level of “L” level (logical low level, hereinafter L level).
Through this operation, a signal is output from AND circuit
8120
, the output signal having a value determined by dividing the oscillation frequency of source oscillator
8010
by the preset value.
For example, suppose that a designed oscillation cycle period of source oscillator
8010
is 4 &mgr;sec and a required refresh period is 16 &mgr;sec or shorter. Then, programmable counter
8100
may divide the output frequency from source oscillator
8010
by 4.
In this way, the preset value supplied to programmable counter
8100
is varied in order to change the oscillation cycle period of reference clock Ref.Clk supplied from self-refresh timer
8000
. However, a problem here is that this control is too coarse as detailed below.
Specifically, if any process variations cause the oscillation cycle period of source oscillator
8010
to be longer than a designed period, the divisor should be decreased to 3 for example in order to maintain the refresh period of 16 &mgr;sec or shorter. Otherwise, the self-refresh cycle period is too long in terms of data holding characteristics of memory cells.
However, if the clock frequency of source oscillator
8010
having the oscillation cycle period which is somewhat longer than 4 &mgr;sec is divided by 3 as described above, the refresh cycle period would be 12 &mgr;sec or somewhat longer. In other words, in spite of the designed self-refresh cycle period of 16 &mgr;sec, the refresh frequency is four-thirds ({fraction (4/3)}) of the required frequency.
On the other hand, if the oscillation cycle period of source oscillator
8010
becomes shorter than the designed period, the oscillation cycle period should be 16 &mgr;sec/5, namely, 3.2 &mgr;sec, or shorter. Otherwise, the divisor cannot be increased in terms of data holding characteristics mentioned above and consequently, the refresh frequency increases.
A resultant problem is thus increase in the amount of current consumed for data retention, in both of the situations in which the oscillation cycle period of source oscillator
8010
is longer and shorter respectively.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a dynamic semiconductor memory device having a self-refresh timer tuned after a wafer process. A flexible tuning is possible under the influence of process variations occurring in the process for forming the self-refresh timer, and increase in the amount of current consumed for data retention can be avoided.
In summary, the present invention is a dynamic semiconductor memory device including a memory cell array, a memory cell selector circuit and a refresh control circuit.
The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell selector circuit selects a memory cell to be refreshed in the memory cell array. The refresh control circuit supplies a first address signal to the memory cell selector circuit for a normal operation, the first address signal corresponding to an externally supplied address, and supplies a second address signal to the memory cell selector ci

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