Dynamic semiconductor memory device superior in refresh...

Details Dynamic semiconductor memory device superior in refresh... Dynamic semiconductor memory device superior in refresh...

2001-03-01

2002-09-17

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S051000, C365S063000

Reexamination Certificate

active

06452859

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a structure for reducing power consumption of a semiconductor memory device. More particularly, the present invention relates to a structure for reducing power consumption of an embedded DRAM (Dynamic Random Access Memory) employed in a system LSI.
2. Description of the Background Art
In a system LSI having a DRAM integrated together with the logic of a processor or an ASIC (Application Specific IC) on a common chip, the DRAM is connected with the logic through a multibit internal data bus of 128 bits to 512 bits, for example. This internal data bus is formed of an on-chip line having parasitic capacitance and parasitic resistance smaller than those of on-board lines, and can implement higher speed data transfer than that of a general-purpose high speed DRAM. In contrast to the structure where a general-purpose DRAM is provided outside the logic and connection therebetween is provided via on-board lines, the number of external data input/output pin terminals of the logic can be reduced in the system LSI. Also, the load capacitance of the data bus lines between the logic and the DRAM can be reduced at least one order. Therefore, the system LSI can significantly reduce current consumption. By virtue of these advantages, the system LSI contributes greatly to the high performance of information equipment handling a large amount of data as in three dimensional graphic processing, image and audio processing, or the like.
FIG. 67
schematically shows an entire structure of a conventional embedded DRAM employed in a system LSI. Referring to
FIG. 67
, the conventional embedded DRAM includes a plurality of memory arrays MA
0
-MAn, sense amplifier bands SB
1
-SBn arranged between memory arrays MA
0
-MAn, and sense amplifier bands SB
0
and SBn+1 arranged outside memory arrays MA
0
and MAn. Each of memory arrays MA
0
-MAn is divided into a plurality of memory subarrays MSA by subword driver bands SWDB.
In memory subarray MSA, memory cells are arranged in rows and columns. A subword line SWL is disposed corresponding to each row. In each of memory arrays MA
0
-MAn, a main word line MWL is disposed commonly to the plurality of memory subarrays MSA divided by subword driver bands SWDB. Main word line MWL is arranged corresponding to a predetermined number of subword lines in each memory subarray MSA in a corresponding memory array.
In subword driver band SWDB, a subword driver is arranged corresponding to subword line SWL. This subword driver drives a corresponding subword line to a selected state according to a signal on a corresponding main word line MWL and a subdecode signal not shown.
In each of sense amplifier bands SB
0
-SBn+1, a sense amplifier circuit is arranged corresponding to a column of a corresponding memory array. Each of sense amplifier bands SB
1
-SBn is shared between adjacent memory arrays. Corresponding to each of memory arrays MA
0
-Man, there are arranged a row decoder for selecting a main word line according to a row address signal and a column decoder arranged in alignment with the row decoder to transmit on a column select line CSL a column select signal for selecting a column from a corresponding memory array according to a column address signal. Column select line CSL is arranged at the sense amplifier band and connects a predetermined number of sense amplifier circuits to a group of global data line pairs GIOP when selected. A predetermined number of global data line pairs GIOP are disposed extending over memory arrays MA
0
-MAn and each coupled with a selected sense amplifier circuit via a local data line pair LIO. By arranging a row decoder and a column decoder in alignment in row/column decoder band RCDB, the distance of transferring a column select signal through column select line CSL can be reduced to realize a high speed column selection. 128 bits to 512 bits global data line pair GIOP are provided, and coupled to a data path band DPB including a preamplifier and a write driver. In this data path band DPB, a preamplifier and write driver are arranged corresponding to each global data line pair GIOP. Global data line pair GIOP may be a data line pair that transmits both read and write data, or may be formed into a read data bus line pair transmitting read data and a separate write data line pair transmitting write data.
The embedded DRAM further includes a row address input circuit/refresh counter RAFK and a column address input circuit CAK receiving an external address of, for example, 13 bits, A
0
-A
12
, applied from the logic, a command decoder/control circuit CDC receiving an external control signal applied from the logic to generate an internal control signal specifying a designated operation, and a data input/output controller DIOK for transferring data between data path band DPB and the logic.
Command decoder/control circuit CDC receives a clock signal CLK, a clock enable signal CKE, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM to determine an operation mode specified according to the logic states of these control signals CKE, /RAS, /CAS, /WE and DM at the rising edge of clock signal CLK. Here, “command” is represented by a combination of the logic states of these control signals CKE, /RAS, /CAS, /WE and DM at the rising edge of clock signal CLK. Data mask signal DM designates a write mask on a byte-by-byte basis for data applied to data input/output controller DIOK.
Command decoder/control circuit CDC decodes a command applied from the logic to generate an operation mode designation signal designating an operation mode instructed by this command to generate various internal control signals required for carrying out the designated operation mode. As a command, there are prepared a row active command to set a row to a selected state, a read command to designate data readout, a write command to designate data writing, a precharge command to place a selected row in a non-selected state, an auto refresh command to carry out a refresh operation, and a self refresh command to carry out self refresh, and the like.
In response to application of a row active command, row address input circuit/refresh counter RAFK accepts external address bits A
0
-A
12
as the row address to generate an internal row address signal under control of command decoder/control circuit CDC. Row address input circuit/refresh counter RAFK includes an address buffer for buffering the applied address bits, and an address latch for latching the signals output from the buffer circuit. Refresh counter is also included in row address input circuit/refresh counter RAFK, to generate a refresh address specifying a refresh row when an auto refresh command or a self refresh command is applied. When the refresh operation is completed, the count value of the refresh counter is incremented or decremented.
Column address input circuit CAK accepts, in response to a read command or a write command, predetermined external address bits, for example, lower external address bits A
0
-A
4
to generate an internal column address signal under control of command decoder/control circuit CDC. Column address input circuit CAK includes an address buffer and an address latch.
The internal row address signal from row address input circuit/refresh counter RAFK is applied to row predecoder RPD. The internal column address signal from column address input circuit CAK is applied to column predecoder CPD. Row predecoder RPD predecodes an applied row address signal to apply a predecoded signal to the row decoder in row/column decoder band RCDB. Column predecoder CPD predecodes an internal column address signal from column address input circuit CAK to apply a predecoded signal to the column decoder in row/column decoder band RCDB.
Upon receiving a read command or a write command, command decoder/control circuit CDC generates an internal control signal to control the operation of the preamplifier or w

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