Dynamic semiconductor memory device on SOI substrate

Details Dynamic semiconductor memory device on SOI substrate Dynamic semiconductor memory device on SOI substrate

1996-11-06

1998-12-15

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 71, 257509, 36518909, H01L 2978, H01L 27108

Patent

active

058500901

ABSTRACT:
In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an "L" level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.

REFERENCES:
patent: 5032891 (1991-07-01), Takagi et al.
patent: 5495439 (1996-02-01), Morihara
"Ulsi Dram/Simoz with Stacked Capacitor Cells for Low-Voltage Operation", T. Eimori et al., IEDM 1993, pp. 45-38.

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