Dynamic semiconductor memory device having separate read and wri

Details Dynamic semiconductor memory device having separate read and wri Dynamic semiconductor memory device having separate read and wri

1992-08-28

1994-06-21

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

365149, 36518901, G11C 700, G11C 1140

Patent

active

053233492

ABSTRACT:
Separated IO type dynamic memory device includes a write data bus for transmitting data to be written into a selected memory cell and a read data bus for transferring data read out from a selected memory cell. The write data bus and the read data bus are separately provided from each other. The memory device further includes a load circuit for supplying a current flow to the read data bus and for precharging the read data bus to a predetermined potential, and drive circuits provided for each pair of bit lines each connecting memory cells of a column for driving the read data bus to a potential corresponding to potentials appearing on an associated pair of bit lines in response to a column select signal. The memory device further includes an insulated gate type transistor inserted on the read data bus between the loading circuit and the driving circuits and receives a predetermined intermediate potential at the gate. An output node for supplying an output data is provided between the insulated gate type transistor and the load circuit. This enables fast discharging of the read data bus at the output node, resulting in a high speed data reading operation.

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