Dynamic semiconductor memory device having a trench capacitor

Details Dynamic semiconductor memory device having a trench capacitor Dynamic semiconductor memory device having a trench capacitor

2000-09-12

2004-04-13

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000

Reexamination Certificate

active

06720606

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor memory devices and methods of manufacturing the same and, more particularly, to highly integrated dynamic memory devices and methods of manufacturing the same.
DESCRIPTION OF THE RELATED ART
FIGS. 1A and 1B
illustrate a memory cell having a MINT architecture and a 0.25 micron design rule which is usable in a 256 Mbit dynamic random access memory (DRAM) device. Specifically,
FIG. 1A
is a top-down view of the trench memory cell and
FIG. 1B
is a cross-sectional view taken along line A-A′ of FIG.
1
A. DRAM cell
550
includes a trench capacitor
555
and a MOS transfer gate
560
. Trench capacitor
555
includes a first N+-type polycrystalline silicon fill
565
, a second polycrystalline silicon fill
567
, and a collar oxide
571
. Transfer gate
560
includes N-type source/drain and drain/source regions
573
and
574
formed in P-type well
575
and a WSix/polycrystalline silicon gate
577
insulatively spaced from the channel region between source/drain region
573
and drain/source region
574
. A bit line contact
579
formed in an opening in an insulating layer
80
(of BPSG, for example) and in insulating layer
578
(of silicon nitride, for example) electrically connects source/drain region
573
to bit line
581
. A shallow trench isolation (STI) structure
590
electrically isolates DRAM cell
550
from an adjacent DRAM cell and passing word line
592
. Passing word line
592
has a WSix/polycrystalline silicon structure. A dielectric layer
587
is formed on bit line
581
and aluminum wirings
589
are formed on dielectric layer
587
. One of the aluminum wirings
589
is connected to bit line
581
by a contact stud
591
of tungsten, for example. A diffusion region
583
electrically connects third polycrystalline silicon fill
569
and drain/source region
574
of MOS transfer gate
560
. This diffusion region is formed by outdiffusing dopants from the highly doped polycrystalline silicon fill in the storage trench into P-well
575
. Diffusion region
583
and third polycrystalline silicon fill
569
constitute a buried strap for connecting trench capacitor
555
to transfer gate
560
.
While the memory cell structure of
FIGS. 1A and 1B
has been successfully applied to 256 Mbit DRAM devices, certain problems can adversely impact the manufacturing yield of such devices. With reference to
FIG. 2A
, the outdiffusion of dopants to form diffusion region
583
must be carefully controlled. If the dopants diffuse too far into the semiconductor substrate, the operation of transfer gate
550
can be adversely affected. This, for example, places certain limitations on the thermal processes used in the manufacturing process since long, high temperature processes will cause a greater outdiffusion of the dopants. In addition, various crystal defects can be generated at the intersection of the active area (transfer gate) and the deep trench. For example, various oxidation processes during the manufacturing process can cause expansion of the collar oxide
571
. This expansion can lead to dislocations in the silicon. In addition to contributing to the adverse operation of the transfer gate, such dislocations can cause junction leakage from the buried strap diffusion layer
583
. Still further, as shown in
FIG. 2B
, in some cases, there can be a discontinuity between the cell array junction and the buried strap caused by ion implantation shadowing due to a passing word line.
Problems are also associated with the scaling-down of the DRAM cell of
FIGS. 1A and 1B
to form more highly integrated memory devices (e.g., 1 Gbit and 4 Gbit DRAM devices). In particular, the scaled-down memory cell must nonetheless provide a capacitor having a size (i.e., a capacitance) for storing a charge which is sufficient to ensure that data may be correctly written to and read out from the memory cell. Since scaling-down generally results in a shrinking of the horizontal dimensions of the memory cell, one possible way to provide a sufficiently-sized capacitor would be to increase the depth of the trench within which the capacitor is formed. In this way, the horizontal dimensions of capacitor may be scaled down while providing a capacitor of the same size or at least scaled down to a lesser degree. However, the high aspect ratios associated with such deep trenches create difficulties in the processes needed to fill the trenches. In short, to increase the size of trench capacitor
555
during scale-down, either the depth of the trench or the horizontal dimensions of the trench must be increased. Since increasing the depth suffers from processing problems as described above and since increasing the horizontal dimensions is contrary to scaling-down goal, it is difficult to increase the integration density of memory cells having the memory cell structure shown in
FIGS. 1A and 1B
for new generations memory devices.
One solution to this scaling-down problem is to overlap the transistor area and the deep trench area. Such a transistor over capacitor (TOC) arrangement is shown in U.S. Pat. No. 4,649,625 to Lu, which is incorporated herein by reference. In this structure, the transfer gate is formed on epitaxial silicon which has been laterally grown over an insulator formed on the deep trench. Such laterally grown epitaxial silicon often suffers from defects which can adversely affect the operating characteristics of the transistor and thus of the memory cell itself.
It would be desirable to provide semiconductor memory devices and methods of manufacturing the same which overcome these and other problems.
SUMMARY OF THE INVENTION
A semiconductor memory device according to a first aspect of the present invention includes a semiconductor substrate, a first semiconductor region of a first conduction type formed on the semiconductor substrate, and a second semiconductor region of a second conduction type opposite to the first conduction type, formed on the first semiconductor region. A trench capacitor having a trench extending through the first semiconductor region and the second semiconductor region is formed such that its top does not reach a top surface of the second semiconductor region, the trench being formed therein with a conductive trench fill. A pair of gate electrodes are formed on the second semiconductor region, each positioned overlying the trench capacitor. A pair of insulating layers are formed to cover each of the pair of gate electrodes. A conductive layer is formed between the pair of insulating layers to self-align to each of the pair of insulating layers. The conductive layer has a leading end insulated from the second semiconductor region and reaching the interior of the second semiconductor region, and is electrically connected to the conductive trench fill of the trench capacitor. A pair of third semiconductor regions of the first conduction type are formed in the second semiconductor region, and positioned opposite to each other with respect to the conductive layer. Each of the third semiconductor regions is directly in contact with the conductive layer, and constitutes either a source or a drain of transistors having one of the pair of gate electrodes, respectively. The pair of third semiconductor regions is formed substantially to a uniform depth.
A semiconductor memory device according to a second aspect of the present invention includes a semiconductor substrate, a plurality of trench capacitors formed in the semiconductor substrate and arranged at a regular pitch, and a semiconductor layer formed on the semiconductor substrate in which the trench capacitors are formed. A element isolation insulating film is buried in the semiconductor layer to define a plurality of active element areas each spreading over two adjacent trench capacitors. A plurality of transistors are formed two by two in each of the active element areas, such that two transistors share one of source/drain diffusion layers, and the other of the source/drain diffusion layers is positioned over regions of two adjacent trench

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