Dynamic semiconductor memory device having a trench capacitor

Details Dynamic semiconductor memory device having a trench capacitor Dynamic semiconductor memory device having a trench capacitor

1997-12-02

2001-05-22

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S304000, C257S311000, C438S244000, C438S248000

Reexamination Certificate

active

06236079

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to semiconductor memory devices and methods of manufacturing the same and, more particularly, to highly integrated dynamic memory devices and methods of manufacturing the same.
DESCRIPTION OF THE RELATED ART
FIGS. 1A and 1B
illustrate a memory cell having a MINT architecture and a 0.25 micron design rule which is usable in a 256 Mbit dynamic random access memory (DRAM) device. Specifically,
FIG. 1A
is a top-down view of the trench memory cell and
FIG. 1B
is a cross-sectional view taken along line A-A′ of FIG.
1
A. DRAM cell
50
includes a trench capacitor
55
and a MOS transfer gate
60
. Trench capacitor
55
includes a first N
+
-type polycrystalline silicon fill
65
, a second polycrystalline silicon fill
67
, and a collar oxide
71
. Transfer gate
60
includes N-type source/drain and drain/source regions
73
and
74
formed in P-type well
75
and a WSix/polycrystalline silicon gate
77
insulatively spaced from the channel region between source/drain region
73
and drain/source region
74
. A bit line contact
79
formed in an opening in an insulating layer
80
(of BPSG, for example) and in insulating layer
78
(of silicon nitride, for example) electrically connects source/drain region
73
to bit line
81
. A shallow trench isolation (STI) structure
90
electrically isolates DRAM cell
50
from an adjacent DRAM cell and passing word line
92
. Passing word line
92
has a WSix/polycrystalline silicon structure. A dielectric layer
87
is formed on bit line
81
and aluminum wirings
89
are formed on dielectric layer
87
. One of the aluminum wirings
89
is connected to bit line
81
by a contact stud
91
of tungsten, for example. A diffusion region
83
electrically connects third polycrystalline silicon fill
69
and drain/source region
74
of MOS transfer gate
60
. This diffusion region is formed by outdiffusing dopants from the highly doped poly-crystalline silicon fill in the storage trench into P-well
75
. Diffusion region
83
and third poly-crystalline silicon fill
69
constitute a buried strap for connecting trench capacitor
55
to transfer gate
60
.
While the memory cell structure of
FIGS. 1A and 1B
has been successfully applied to 256 Mbit DRAM devices, certain problems can adversely impact the manufacturing yield of such devices. With reference to
FIG. 2A
, the outdiffusion of dopants to form diffusion region
83
must be carefully controlled. If the dopants diffuse too far into the semiconductor substrate, the operation of transfer gate
50
can be adversely affected. This, for example, places certain limitations on the thermal processes used in the manufacturing process since long, high temperature processes will cause a greater outdiffusion of the dopants. In addition, various crystal defects can be generated at the intersection of the active area (transfer gate) and the deep trench. For example, various oxidation processes during the manufacturing process can cause expansion of the collar oxide
71
. This expansion can lead to dislocations in the silicon. In addition to contributing to the adverse operation of the transfer gate, such dislocations can cause junction leakage from the buried strap diffusion layer
83
. Still further, as shown in
FIG. 2B
, in some cases, there can be a discontinuity between the cell array junction and the buried strap caused by ion implantation shadowing due to a passing wordline.
Problems are also associated with the scaling-down of the DRAM cell of
FIGS. 1A and 1B
to form more highly integrated memory devices (e.g., 1 Gbit and 4 Gbit DRAM devices). In particular, the scaled-down memory cell must nonetheless provide a capacitor having a size (i.e., a capacitance) for storing a charge which is sufficient to ensure that data may be correctly written to and read out from the memory cell. Since scaling-down generally results in a shrinking of the horizontal dimensions of the memory cell, one possible way to provide a sufficiently-sized capacitor would be to increase the depth of the trench within which the capacitor is formed. In this way, the horizontal dimensions of capacitor may be scaled down while providing a capacitor of the same size or at least scaled down to a lesser degree. However, the high aspect ratios associated with such deep trenches create difficulties in the processes needed to fill the trenches. In short, to increase the size of trench capacitor
55
during scale-down, either the depth of the trench or the horizontal dimensions of the trench must be increased. Since increasing the depth suffers from processing problems as described above and since increasing the horizontal dimensions is contrary to scaling-down goal, it is difficult to increase the integration density of memory cells having the memory cell structure shown in
FIGS. 1A and 1B
for new generations memory devices.
One solution to this scaling-down problem is to overlap the transistor area and the deep trench area. Such a transistor over capacitor (TOC) arrangement is shown in U.S. Pat. No. 4,649,625 to Lu, which is incorporated herein by reference. In this structure, the transfer gate is formed on epitaxial silicon which has been laterally grown over an insulator formed on the deep trench. Such laterally grown epitaxial silicon often suffers from defects which can adversely affect the operating characteristics of the transistor and thus of the memory cell itself.
It would be desirable to provide semiconductor memory devices and methods of manufacturing the same which overcome these and other problems.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the present invention, a semiconductor memory device includes a semiconductor substrate and first, second, third and fourth spaced apart word lines formed on the semiconductor substrate and extending in a first direction. First, second, and third spaced apart bits line are formed on the semiconductor substrate and extend in a second direction. An isolated active areas are formed on the semiconductor substrate under the second bit line. A first transfer gate transistor is formed in the active area, the first transfer gate transistor including spaced apart source and drain regions and the second word line being insulatively spaced from a channel region between the source and drain regions. A second transfer gate transistor is formed in the active area, the second transfer gate transistor including spaced apart source and drain regions and the third word line being insulatively spaced from a channel region between the source and drain regions. A first storage node is formed in a portion of the semiconductor substrate which is between the first and second word lines, between the first and second bit lines, under the second bit line, and between the second and third bit line. A second storage node is formed in a portion of the semiconductor substrate which is between the third and fourth word lines, between the first and second bit lines, under the second bit line, and between the second and third bit line.
In accordance with another aspect of the present invention, a semiconductor memory device includes a semiconductor substrate and first, second, third and fourth spaced apart word lines formed on the semiconductor substrate and extending in a first direction. A bit line is formed on the semiconductor substrate and extend in a second direction. An isolated active area is formed on the semiconductor substrate under the bit line. A first transfer gate transistor is formed in the active area, the first transfer gate transistor including spaced apart source and drain regions and the second word line being insulatively spaced from a channel region between the source and drain regions. A second transfer gate transistor is formed in the active area, the second transfer gate transistor including spaced apart source and drain region and the third word line being insulatively spaced from a channel region between the source and drain regions. A first storage node is formed in a portion of the semiconductor s

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