Dynamic semiconductor memory device having a simultaneous test f

Details Dynamic semiconductor memory device having a simultaneous test f Dynamic semiconductor memory device having a simultaneous test f

1984-11-20

1988-05-10

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Testing

365230, G11C 2900

Patent

active

047440619

ABSTRACT:
A dynamic semiconductor memory device including memory cells divided into a plurality of blocks (1-1, 1-2). A simultaneous write enable circuit performs a write operation simultaneously upon the plurality of blocks, and a comparison circuit compares read data of one block with read data of the other block, thereby carrying out a test.

REFERENCES:
patent: 4464750 (1984-08-01), Tatematsu
patent: 4541090 (1985-09-01), Shiragasawa
Patent Abstracts of Japan, vol. 7, No. 253, Nov. 10, 1983 & JP-A-58 13 7178.
Patent Abstracts of Japan, vol. 7, No. 23, Jan. 29, 1983 & JP-A14 57 176 587.
Patent Abstracts of Japan, vol. 5, No. 107, Jul. 11, 1981 & JP-A14 56 51 093.

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