Dynamic semiconductor memory device formed by 2-transistor cells

Details Dynamic semiconductor memory device formed by 2-transistor cells Dynamic semiconductor memory device formed by 2-transistor cells

1988-11-04

1991-04-23

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

36523006, G11C 1140

Patent

active

050105191

ABSTRACT:
An FIFO memory comprises two-transistor type memory cells. Each of the memory cells comprises a first transistor, a second transistor and storage capacitance. The storage capacitance is connected to a first bit line through the first transistor and connected to a second bit line through the second transistor. The first transistor has its gate connected to a first word line, and the second transistor has its gate connected to a second word line. Data is written or read out through the first transistor, and data is read out or written through the second transistor.

REFERENCES:
patent: 4044340 (1977-08-01), Itoh
"Introduction to NMOS and CMOS VLSI System Design", pp. 268-273.
K. L. Anderson, "Shared Bit Line Sensing for Two-Device Cell", IBM Technical Disclosure Bulletin, vol. 20, No. 11A, (Apr. 1978), pp. 4295-4296.

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