DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING...

Details DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING... DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING...

2001-03-27

2002-09-10

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230060, C365S230030, C365S201000, C365S202000, C365S203000, C365S205000, C365S208000, C365S207000, C365S206000, C365S190000, C365S196000, C365S194000, C365S189090, C365S189110, C365S236000, C365S227000

Reexamination Certificate

active

06449204

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a configuration for reducing power consumption of a semiconductor memory device. More particularly, the present invention relates to a configuration for reducing power consumption of an embedded type DRAM (dynamic random access memory) used in a system LSI.
2. Description of the Background Art
In a system LSI constituted of DRAM and a logic such as a processor, ASIC (application specific integrated circuit) or the like in a merged manner, DRAM and the logic are interconnected to each other using an internal data bus of multiple bits such as 128 bits to 512 bits. This internal data bus is on-chip interconnection lines, and a parasitic capacitance and a parasitic resistance thereof are small as compared with those of on-board interconnection lines. Therefore, such a system LSI can achieve a high data transfer speed as compared with a general-purpose high speed DRAM. Furthermore, as compared with a configuration in which a general-purpose DRAM is mounted external to a logic and both are interconnected through on-board interconnection lines, the number of external data input/output pin terminals of the logic can be decreased and a load capacitance of a data bus line between the logic and DRAM can also be reduced by more than one order of magnitude. Therefore, this system LSI can decrease a consumed current greatly. Owing to these advantages, a system LSI has largely contributed to improvement of a performance of information equipment handling a great amount of data such as those in three-dimensional graphic processing, image and speech processing and others.
FIG. 96
is a diagram schematically showing a configuration of a whole of a conventional embedded DRAM used in a system LSI. In
FIG. 96
, the embedded DRAM includes: a plurality of memory cell arrays MA
0
to MAn; sense amplifier bands SB
1
to SBn each arranged between the memory cell arrays MA
0
to MAn; and sense amplifier bands SB
0
and SBn+1 arranged outside the respective memory cell arrays MA
0
and MAn. Each of the memory cell arrays MA
0
to MAn is divided into a plurality of memory cell sub arrays MSA by sub word driver bands SWDB.
In a memory cell sub array MSA, memory cells are arranged in rows and columns, and sub word lines SWL are provided corresponding to respective rows. A main word line MWL is commonly provided to memory cell sub arrays MSA divided by the sub word driver bands SWDB A in a memory array MA. Main word lines MWL are each provided corresponding to a prescribed number of sub word lines in a memory cell sub array MSA.
In a sub word driver band SWDB, sub word drivers are provided corresponding to the sub word lines SWL. Each sub word driver drives a corresponding sub word line to a selected state according to a signal on a corresponding main word line MWL and a sub decode signal, not shown.
In each of the sense amplifier bands SB
0
to SBn+1, sense amplifier circuits are provided corresponding to the columns of a corresponding memory cell array. Each sense amplifier circuit of the sense amplifier bands SB
1
to SBn is shared between adjacent memory cell arrays. Row decoders each selecting a main word line according to a row address signal are provided corresponding to the respective memory cell arrays MA
0
to MAn, and column decoders transmitting a column select signal for selecting a column in a memory cell array according to a column address signal onto a column select line CSL are provided in alignment with the row decoders. Column select lines CSL are provided in respective sense amplifier bands and each connect a prescribed number of sense amplifier circuits to a group of internal data bus line pairs GIOP when selected.
The internal data bus line pairs GIOP are arranged extending over the memory arrays MA
0
-Man in a column direction. A prescribed number of internal data line pairs GIOP are coupled with selected sense amplifier circuits through local data lines LIO. Row decoders and column decoders are arranged in alignment in a row/column decoder band RCDB, and a propagation distance of a column select signal on a column select line CSL is decreased to achieve high speed column selection.
Internal data line pairs GIOP are provided by 128 bits to 512 bits or more and coupled with a data path band DPB including preamplifiers and write drivers. In the data path band DPB, the preamplifiers and the write drivers are provided corresponding to respective global data line pairs GIOP. A global data line pair GIOP may be a data line pair transmitting both of write data and read data, or may include a bus line pair transmitting read data and a write data line pair transmitting write data may be used independently of each other.
The embedded DRAM further includes: a row address circuit/refresh counter RAFK, a column address input circuit CAK receiving an external address A
0
to A
12
of, for example, 13 bits applied from a logic; a command decoder/control circuit CDC receiving external control signals applied from the logic to generate internal control signals specifying various operations; and a data input/output controller DIOK for performing transfer of data between the data path band DPB and the logic.
The command decoder/control circuit CDC receives a clock signal CLK, a clock enable signal CKE, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM, and determines an instructed operating mode according to logical states of the control signals CKE, /RAS, /CAS, /WE and DM at a rising edge of the clock signal CLK. The term “command” indicates a combination of logical states of the plurality of control signals CKE, /RAS, /CAS and /WE at a rising edge of the clock signal CLK. The data mask signal DM instructs write masking, with a byte being a unit, for data applied to the data input/output controller DIOK. The command decoder/control circuit CDC decodes a command applied from the logic to generate an operating mode instructing signal instructing an operating mode specified by the command and furthermore generates various internal control signals for performing the specified operating mode. Commands include: a row active command for setting a row to a selected state; a read command instructing data reading; a write command instructing data writing; a precharge command for placing a selected row in a non-selected state; an auto-refresh command for performing a refresh operation; and a self refresh command for performing self refresh of storage data.
The row address input circuit/refresh counter RAFK takes in external address bits A
0
to A
12
as a row address under control of the command decoder/control circuit CDC, when a row active command is supplied, to generate an internal row address. The row address input circuit/refresh counter RAFK includes: an address buffer for buffering received address bits; and an address latch for latching an output signal of the buffer circuit. A refresh counter included in the row address input circuit/refresh counter RAFK generates a refresh address specifying a refresh row when an auto-refresh command or a self-refresh command is supplied. A count value of the refresh counter is incremented or decremented each time the refresh operation is completed. The column address input circuit CAK takes in, for example, lower external address bits A
0
to A
4
to generate an internal column address signal under control of the command decoder/control circuit CDC when a read command or a write command is supplied. The column address input circuit CAK also includes an address buffer and an address latch.
An internal row address signal from the row address input circuit/refresh counter RAFK is applied to a row predecoder RPD, while an internal column address signal from the column address input circuit CAK is applied to a column predecoder CPD. The row predecoder RPD predecodes the received row address signal to apply the predecoded signal to a row decoder included in

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