Dynamic semiconductor memory device and method of testing the sa

Details Dynamic semiconductor memory device and method of testing the sa Dynamic semiconductor memory device and method of testing the sa

1997-08-13

2000-07-11

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

36518901, 365201, G11C 2900, G11C 700

Patent

active

060888199

ABSTRACT:
In a DRAM, a boosted voltage Vpp is applied to a selected word line WL1 in a normal mode. In a test mode, a power supply voltage Vcc at a level lower than Vpp level is applied onto selected word line WL1. High data written into memory cell in the test mode of the DRAM is at the level lower than that of the high data written into memory cell in the normal mode. Therefore, a time before an H.fwdarw.L error occurs can be reduced, and a test time can be reduced.

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patent: 5140553 (1992-08-01), Choi et al.
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