Dynamic semiconductor memory device

Details Dynamic semiconductor memory device Dynamic semiconductor memory device

1992-08-18

1993-04-13

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365 51, G11C 1124

Patent

active

052028496

ABSTRACT:
A dynamic random access memory comprises a substrate, a transfer transistor provided on the substrate, a memory cell capacitor provided on the substrate in contact with a first diffusion region formed in the substrate, a first conductor pattern provided on the substrate to extend in a first direction as a word line, a first insulator layer provided on the substrate to bury the memory cell capacitor and the first conductor pattern, a first contact hole provided on the first insulator layer to expose a second diffusion region formed in the substrate, a second conductor pattern provided on the first insulator layer to extend in a second direction, passing above the memory cell capacitor and making a contact with the second diffusion region at the first contact hole, a second insulator layer provided on the second conductor pattern, a second contact hole provided on the second insulator layer at a part thereof that locates above the memory cell capacitor to expose the upper major surface of the second conductor pattern, and a third conductor pattern provided on the second insulator layer to extend in the second direction substantially coincident with the first conductor pattern as a bit line of the dynamic random access memory, wherein the third conductor pattern makes a contact with the second conductor pattern at the second contact hole.

REFERENCES:
patent: Re33261 (1990-07-01), Baglee et al.
Patent Abstracts of Japan, vol. 13, No. 416 (E-821) [3764], Sep. 14, 1989; & Drawings of JP-A 1-155656.
"An Optically Delineated 4.2-.mu.m.sup.2 Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell", Kimura et al., IEEE Transactions on Electron Devices, vol. 35, No. 10, Part I, Oct., 1988, pp. 1591-1595.

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