Dynamic semiconductor memory device

Details Dynamic semiconductor memory device Dynamic semiconductor memory device

1986-03-27

1988-03-22

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365149, 365208, G11C 700

Patent

active

047333740

ABSTRACT:
A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.

REFERENCES:
patent: 4025907 (1977-05-01), Karp et al.
patent: 4045783 (1977-08-01), Harland
patent: 4476547 (1984-10-01), Miyasaka
Japanese Patent Publication (Kokoku) No. 55-39073, Oct. 8, 1980.
Furuyama et al., "A Vertical Capacitor Cell for ULSI DRAM's," Symposium on VLSI Technology, pp. 16-17, Sep. 1984.
Wada et al., "A Folded Capacitor Cell (F.C.C.) for Future Megabit DRAMs," IEDM Technical Digest, pp. 244, 247, 1984.

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