Dynamic semiconductor memory device

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S207000

Reexamination Certificate

active

07106641

ABSTRACT:
To provide a dynamic semiconductor memory device wherein it is possible to perform a reliable redundancy relief with a small layout area and high redundancy relieving rate while properly dealing with the standby current fault caused by a short-circuit defect between a bit line and word line. A common current-limiting element is provided for an equalizer circuit for a bit line pair on one side and another equalizer circuit for another bit line pair on the other side in a shared sense amplifier, and a bit line precharge potential is supplied to the equalizer circuits on the both sides through the current-limiting element.

REFERENCES:
patent: 5499211 (1996-03-01), Kirihata et al.
patent: 5594701 (1997-01-01), Asaka et al.
patent: 5689469 (1997-11-01), Asaka
patent: 5748520 (1998-05-01), Asaka et al.
patent: 5896336 (1999-04-01), McClure
patent: 6882591 (2005-04-01), Winograd et al.
patent: 7-334987 (1995-12-01), None
patent: 8-263983 (1996-10-01), None
T. Kirihata et al., “Fault-Tolerant Designs for 256 Mb DRAM,” IEEE Journal of Solid-State Circuits, vol. 31:4, Apr. 1996, pp. 558-566.

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