Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-09-12
2006-09-12
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S207000
Reexamination Certificate
active
07106641
ABSTRACT:
To provide a dynamic semiconductor memory device wherein it is possible to perform a reliable redundancy relief with a small layout area and high redundancy relieving rate while properly dealing with the standby current fault caused by a short-circuit defect between a bit line and word line. A common current-limiting element is provided for an equalizer circuit for a bit line pair on one side and another equalizer circuit for another bit line pair on the other side in a shared sense amplifier, and a bit line precharge potential is supplied to the equalizer circuits on the both sides through the current-limiting element.
REFERENCES:
patent: 5499211 (1996-03-01), Kirihata et al.
patent: 5594701 (1997-01-01), Asaka et al.
patent: 5689469 (1997-11-01), Asaka
patent: 5748520 (1998-05-01), Asaka et al.
patent: 5896336 (1999-04-01), McClure
patent: 6882591 (2005-04-01), Winograd et al.
patent: 7-334987 (1995-12-01), None
patent: 8-263983 (1996-10-01), None
T. Kirihata et al., “Fault-Tolerant Designs for 256 Mb DRAM,” IEEE Journal of Solid-State Circuits, vol. 31:4, Apr. 1996, pp. 558-566.
Elpida Memory Inc.
Foley & Lardner LLP
Le Vu A.
LandOfFree
Dynamic semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3529991