Dynamic semiconductor memory device

Details Dynamic semiconductor memory device Dynamic semiconductor memory device

1990-05-11

1992-02-25

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Noise suppression

365207, 36518901, 365 63, G11C 1300

Patent

active

050918877

ABSTRACT:
A dynamic semiconductor memory device includes a memory cell array comprising a plurality of word lines (WL.sub.0 -WL.sub.n), a plurality of bit lines (BL.sub.n -BL.sub.n+11) and a plurality of memory cells (MC) connected to intersections between the word lines and the bit lines. The plurality of bit lines include bit line pairs of two bit lines, one being a bit line for reading information of a memory cell, and the other being a bit line for providing a reference potential, and sense amplifiers (SA1-SA5) for detecting a potential difference between each bit line pair to amplify the same. The plurality of bit line pairs include bit line pairs crossing with each other such that a capacitance is balanced between adjacent bit lines, and bit line pairs having no crossing portion between which the bit line pairs crossing with each other are arranged such that a capacitance is balanced between said adjacent bit lines. Accordingly, the bit lines having the crossing portions receive the same noise from the other adjacent bit lines, and the bit lines having no crossing portion receive no noise between the paired bit lines, so that a reading potential difference can be reduced.

REFERENCES:
patent: 3942164 (1976-03-01), Dunn
patent: 5001669 (1991-03-01), Cho et al.
Tsutomu Yoshihara et al., "A Twisted Bit Line Technique for Multi-Mb DRAMs", Digest of Technical Papers 1988, IEEE International Solid-State Circuits Conference (Feb. 1988) pp. 238, 239.
yasuji Nagayama et al., "Second Generation 1M-Bit Dynamic CMOS RAM" Mitsubishi Electric Company Technical Journal, vol. 62, No. 7 (1988) pp. 76-81.

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