Dynamic semiconductor memory device

Details Dynamic semiconductor memory device Dynamic semiconductor memory device

1994-08-31

1996-07-16

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Capacitors

365 63, 365190, G11C 700

Patent

active

055373470

ABSTRACT:
A NAND-type dynamic semiconductor memory device having a folded bit architecture which reduces chip size and decreases array noise and soft error. The device is comprised of a plurality of memory cell groups, each group comprised of a plurality of bit memory cells connected in series, each bit memory cell having a MOS transistor and a capacitor. Two adjacent memory cell groups are connected respectively to one of a pair of bit lines. Each bit line is coupled respectively to a first one of the transistors located at the end of each memory cell group. A pair of first word lines are coupled respectively to the gates of the first one of the transistors coupled to the paired bit lines. A plurality of second word lines are each commonly coupled to the gates of corresponding ones of the transistors of the memory cell groups coupled to the paired bit lines.

REFERENCES:
patent: 5341326 (1994-08-01), Takase et al.
patent: 5369612 (1994-11-01), Furuyama
"A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture", Kimura et al., Digest of Technical Papers, ISSCC 91, pp. 106-107 & 297, Feb. 14, 1991.
"An Experimental DRAM with a NAND-Structured Cell", Hasegawa et al., Digest of Technical Papers, ISSCC 93, pp. 46-47, Feb. 24, 1993.

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