Dynamic semiconductor memory and manufacturing method thereof

Details Dynamic semiconductor memory and manufacturing method thereof Dynamic semiconductor memory and manufacturing method thereof

1983-06-22

1985-09-24

James, Andrew J.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

357 2313, 357 59, 156643, H01L 2978, H01L 2904

Patent

active

045435979

ABSTRACT:
A method to prevent dielectric breakdown of a thin gate insulating film of a memory cell capacitor of a dynamic semiconductor memory device such as a dynamic random access memory during fabrication of the memory. A diffusion layer of an n-conductivity type is formed on a predetermined surface region of a semiconductor substrate of a p-conductivity type so as to form a p-n junction. Then, there is formed a polycrystalline semiconductor layer which corresponds to a gate electrode and which is connected to the thin gate insulating film and partially contacts the diffusion layer. Thus the polycrystalline semiconductor layer is electrically connected to the substrate through a diode region which is formed of the p-n junction. The polycrystalline semiconductor layer is then etched in a reactive ion etching step, and any abnormal charges stored in the thin gate insulation layer during the reactive etching step are immediately discharged to the substrate.

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IBM Technical Disclosure Bulletin, vol. 13#10, p. 2847 by Enenidis, Mar. 1971.
IBM Technical Disclosure Bulletin, vol. 20 #11A, Apr. 1978, "FET Device Manufacturing Process" by Fortino et al.

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