Dynamic scheduler for time multiplexed serial bus

Details Dynamic scheduler for time multiplexed serial bus Dynamic scheduler for time multiplexed serial bus

1997-06-23

1999-08-03

Sheikh, Ayaz R.

39520071, G06F 1300

Patent

active

059336110

ABSTRACT:
Method and apparatus for improving bus utilization on a bus having a tiered topology, by estimating the worst-case transaction duration time for executing a transaction. The sum of three delays D.sub.fixed, D.sub.data and D.sub.hub.sbsb.--.sub.depth, is detemined, where D.sub.fixed is a delay component which can depend on the transmission duration type of the transaction, as well as other fixed delays; D.sub.data is a delay component which depends on a number N.sub.bytes of bytes to be transmitted for the transaction, and D.sub.hub.sbsb.--.sub.depth is a delay component which depends (in one aspect) on the actual maximum hub depth in the bus topology, or which depends (in another aspect) on the actual hub depth of the target device.

REFERENCES:
patent: 4517641 (1985-05-01), Pinheiro
patent: 5390351 (1995-02-01), Di Giulio et al.
patent: 5699519 (1997-12-01), Shiobara
patent: 5745758 (1998-04-01), Shaw et al.
patent: 5774654 (1998-06-01), Maki
Compaq Computer Corp., et al., "Universal Serial Bus Specification", Rev. 1.0 (Jan. 15, 1996).

Affiliated with

Also associated with

Rating

Dynamic scheduler for time multiplexed serial bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dynamic scheduler for time multiplexed serial bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic scheduler for time multiplexed serial bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-857919