Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-30
2001-04-10
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06216192
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to communication from one bus to another via bus bridges.
BACKGROUND OF THE INVENTION
Many computers now employ a mezzanine bus that allows high speed communication between the processor, memory, and peripheral devices. These computers generally also provide bridges to other, often older, types of buses. Providing these bridges can allow the processor to communicate efficiently with devices employing specialized interfaces, with legacy devices that use older bus interfaces, and with slower or less expensive devices that do not need to communicate at high speeds.
The bridges provided on existing computers do not always use consistent access methods, even when two or more are connected to the same bus. For example, bridges between a PC Interactive (PCI) mezzanine bus and Industry Standard Architecture (ISA) buses can operate in either positive or subtractive modes. In positive mode, the ISA address space is allocated as a portion of the PCI address space, while in subtractive mode, those requests that are not claimed by the PCI bus can be claimed by the ISA bus.
SUMMARY OF THE INVENTION
Systems according to the invention may be advantageous in that they may permit access requests from a mezzanine bus through different bridges to perform in similar ways, even if the bridges are configured differently. This can make the interface between hardware and software more easy to manage by allowing software to treat peripheral devices attached to different types of bridges as similar devices. The invention may also allow a computer to use more of the features of the peripheral devices or to use the peripheral devices more effectively by evading limitations of the addressing mode for one or more of the bridges.
In one general aspect, the invention features a computer system including a processor having a bus port, a mezzanine bus operatively connected to the bus port, a first peripheral bus, a first bridge operatively connected between the mezzanine bus port and the first peripheral bus, and an input/output handler responsive to the mezzanine bus and operative to intercept a subset of bus accesses from the mezzanine bus to the first peripheral bus.
The computer system can include a second peripheral bus, and a second bridge operatively connected between the mezzanine bus and the second peripheral bus, wherein the bridges employ different addressing modes. The first bridge can employ a positive addressing mode and the second bridge can employ a subtractive addressing mode. The input/output handler can be operative to intercept attempts to dynamically adjust resources allocated to devices on the first peripheral bus. The input/output handler can be operative to reprogram the first bridge in response to intercepted accesses on the mezzanine. The mezzanine bus can be a PCI bus and the first peripheral bus can be an ISA bus.
In one general aspect, the invention features a computer system including means for intercepting access attempts of a first type destined for first circuitry, means responsive to the means for intercepting for decoding the access attempts to obtain information about the nature of the access attempts, and means responsive to the means for decoding for reprogramming the first circuitry in response to the access attempts of the first type in conformance with the information obtained by the means for decoding.
The first circuitry can be a bridge and the bus can be a mezzanine bus. The computer system can further include means for passing access attempts of the first type over a second bridge of the same type as the first bridge. The means for intercepting can intercept attempts to allocate or deallocate resources through the bridge. The means for reprogramming can be operative to decline to reprogram the bridge in response to the information in further access attempts.
In another general aspect, the invention features a method of operating a computer. The method includes steps of intercepting access attempts of a first type from a bus destined for first circuitry, decoding the access attempts to obtain information about the nature of the access attempts, and reprogramming the circuitry in response to the access attempts of the first type in conformance with the information in the access attempts obtained in the step of decoding. The bus can be a mezzanine bus and the first circuitry can be a first bridge and the method can further include the step of passing access attempts of the first type over a second bridge of the same type as the first bridge. The step of intercepting can intercept attempts to allocate or deallocate resources through a bridge. The step of intercepting intercepts can attempt to allocate or deallocate resources through a bridge. The bus can be a mezzanine bus and the first circuitry can be a first bridge and the method can further include steps of intercepting further access attempts, decoding the further access attempts, and declining to reprogram the bridge in response to the information in the further access attempts.
In another general aspect, the invention features a computer system including a processor having a bus port, a bus operatively connected to the bus port, a first circuit having programmable access circuitry operatively connected to the bus port, and an input/output handler responsive to the bus and operative to intercept a subset of bus accesses from the bus to the first circuit and operatively connected to the programmable access circuitry of the first circuit.
REFERENCES:
patent: 5596729 (1997-01-01), Lester et al.
patent: 5864688 (1999-01-01), Santos et al.
Frame Robert C.
Hennessy Richard
Sakarda Premanand
Sawyer Mark
Auve Glenn A.
Compaq Computer Corporation
Hamilton Brook Smith & Reynolds P.C.
LandOfFree
Dynamic resource allocation across bus bridges does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamic resource allocation across bus bridges, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamic resource allocation across bus bridges will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2555074