Dynamic register with low clock rate testing capability

Details Dynamic register with low clock rate testing capability Dynamic register with low clock rate testing capability

2005-08-09

2005-08-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S239000

Reexamination Certificate

active

06928018

ABSTRACT:
A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

REFERENCES:
patent: 3993916 (1976-11-01), Copeland et al.
patent: 4843254 (1989-06-01), Motegi et al.
patent: 5463240 (1995-10-01), Watanabe
patent: 6212119 (2001-04-01), Hatamian
patent: 6456552 (2002-09-01), Hatamian
patent: 6661727 (2003-12-01), Hatamian

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