Dynamic reference voltage calibration integrated FeRAMS

Details Dynamic reference voltage calibration integrated FeRAMS Dynamic reference voltage calibration integrated FeRAMS

2003-05-20

2004-10-12

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189110

Reexamination Certificate

active

06804141

ABSTRACT:

BACKGROUND
Conventional ferroelectric random access memories (FeRAMs) have memory cells containing ferroelectric capacitors. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates, and the polarization state of the ferroelectric material indicates a stored data value. To write a data bit in a memory cell, a write operation applies write voltages to the plates of the ferroelectric capacitor to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed, which in turn maintains a charge on the conductive plates.
A conventional read operation for a FeRAM cell connects one plate of a ferroelectric capacitor to a bit line and raises the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large current and voltage increase on the bit line. A sense amplifier can sense the resulting bit line current or voltage to determine the stored value.
FIG. 1
illustrates a portion of a conventional FeRAM
100
that includes memory cells
110
arranged in rows and columns to form a memory array. Only one column and two rows of memory cells
110
are shown in
FIG. 1
for simplicity of illustration, but a typical FeRAM array may include hundreds or thousands of columns of memory cells with a similar number of rows. Each memory cell
110
of FeRAM
100
includes a ferroelectric capacitor
112
and a select transistor
114
. Each select transistor
114
has a gate connected to a word line
116
corresponding to the row containing the memory cell and a source/drain connected to a bit line
118
corresponding to the column containing the memory cell.
A conventional read operation accessing a selected memory cell
110
in FeRAM
100
biases a plate of the selected memory cell
110
to a plate voltage Vp (e.g., about 3 V), and activates a selected word line
116
to turn on a select transistor
114
thereby electrically connecting the selected ferroelectric capacitor
112
to bit line
118
. The difference between the plate voltage and the initial bit line voltage forces the persistent polarization in the selected ferroelectric capacitor into a first state. Bit line
118
acquires a voltage V
0
or V
1
that depends on the initial polarization state of the selected memory cell
110
. In particular, if the selected memory cell
110
was in a second state having a persistent polarization in a direction opposite to the persistent polarization of the first state, forcing the memory cell from the second state into the first state causes a relatively large current to bit line
118
and a corresponding bit line voltage V
1
. If the selected memory cell was already in the first state, a relatively small current flows to bit line
118
, and the bit line acquires a lower voltage V
0
.
A sense amplifier
130
connected to the bit line
118
compares the bit line voltage V
0
or V
1
to a reference voltage VREF. A reference voltage generator
140
generates reference voltage VREF, which is preferably about halfway between voltages V
0
and V
1
. In sense amplifier
130
, cross-coupled transistors drive bit line
118
to a logic level (high or low) depending on whether the bit line voltage V
0
or V
1
was greater or less than reference voltage VREF. The bit read has a value indicated by the voltage on bit line
118
after operation of sense amplifier
130
.
The generation of reference voltage VREF for comparison to the developed bit line voltage V
0
or V
1
is critical to data integrity. However, the variable properties of ferroelectric capacitors
118
, which are process and time dependent, can make selection of a voltage level for reference voltage VREF difficult. More specifically, ferroelectric capacitors
112
generally differ somewhat from each other due to manufacturing variations and locations across the memory array. As a result, different memory cells
110
generate different voltages when accessed.
FIG. 2
illustrates a distribution of bit line voltage resulting from reading the ferroelectric capacitors in a FeRAM. As illustrated, a histogram
200
of bit line voltages generated when reading FeRAM cells in a first state is bell-shaped and centered at voltage V
0
AVE
. A histogram
210
of bit line voltages generated when reading memory cells in a second state is bell-shaped and centered at voltage V
1
AVE
. Ideally, the reference voltage generator generates a reference voltage VREF that accommodates weak cells, (e.g., cells for which voltage V
1
is relatively low or voltage V
0
is relatively high) so that the weak cells still function, thus giving the highest yield of functional FeRAM circuits.
Factors such as ageing, temperature, and imprint of the FeRAM cells may further shift or change the voltage distributions illustrated in FIG.
2
. The cells that are more frequently accessed degrade or “fatigue” faster than the less frequently accessed cells. The ferroelectric capacitors are also subject to “relaxation” and “imprint.” Relaxation refers to partial loss of remnant charge in a microsecond regime if the ferroelectric capacitor is left unaccessed following a sequence of continuous read/write cycling. Imprint, which appears as a voltage offset in both voltages V
1
and V
0
, refers to the tendency of a ferroelectric capacitor to prefer one state over the other if the FeRAM cell remains in that state for a long period of time. Selecting a reference voltage VREF that can provide the required data integrity over a long useful life of the memory can be difficult.
SUMMARY
In accordance with an aspect of the invention, a reference voltage generator for a FeRAM periodically (e.g., at start up and/or every few minutes during operation) calibrates the reference voltage to track memory cell variation due to factors such as temperature and aging. As a result, the calibrated reference voltage provides high data integrity over an extended life of the FeRAM. Further, the self-calibrating reference voltage generator does not require an initial calibration during fabrication of the FeRAM. Thus, manufacturing or packaging processes such as metal masking or fuse cutting to set the optimal reference voltage for each die are not required.
In accordance with another aspect of the invention, calibration circuitry for the reference voltage can be combined with redundancy circuitry. The calibration circuitry can thus measure a charge distribution for reference voltage selection and during that process identify memory cells that do not provide adequate bit line voltages. The identified memory cells can then be replaced with redundant memory cells on the chip. Dynamic identification of memory cells that become defective can dramatically increase the useful life of the FeRAM.
One specific embodiment of the invention is a memory that includes an array of ferroelectric memory cells, sense amplifiers, a reference voltage generator, and a calibration circuit. The reference voltage generator uses an input value (e.g., a stored digital value) to control the voltage level of a reference signal that the reference voltage generator provides to the sense amplifiers for use when sensing bit lines. The calibration circuit controls a calibration operation that evaluates bit line voltages read out of a set of the ferroelectric memory cells and based on an evaluation result, sets the input value to be used when reading the set of ferroelectric memory cells.
The calibration circuit, in one embodiment, includes a first counter and control logic. The first counter holds a first count that is applied as the input value of the reference voltage generat

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