Dynamic redundancy circuit for memory in integrated circuit form

Details Dynamic redundancy circuit for memory in integrated circuit form Dynamic redundancy circuit for memory in integrated circuit form

1994-09-15

1997-02-18

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 700

Patent

active

056047029

ABSTRACT:
To prompt a repairing operation as and when defective cells appear in an integrated circuit memory, there is provided an auxiliary memory related to a programmable comparator. Whenever the cells of the memory are to be read, the auxiliary memory is read and its content is compared with the address selected in the memory array. The result of this comparison produces, in real time, the addressing signals of a redundant cell and signals for the neutralization of the initially encountered cell. This system can be used more particularly in the field of EEPROM type memories.

REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 4376300 (1983-03-01), Tsang
patent: 4583179 (1986-04-01), Horii et al.
patent: 4701887 (1987-10-01), Ogawa
patent: 4733394 (1988-03-01), Giebel
patent: 4849939 (1989-07-01), Muranaka et al.
patent: 4862416 (1989-08-01), Takeuchi
patent: 5097447 (1992-03-01), Ogawa et al.

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