Dynamic reconfiguration of PCI Express links

Details Dynamic reconfiguration of PCI Express links Dynamic reconfiguration of PCI Express links

2006-08-29

2006-08-29

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S307000, C710S311000, C710S313000

Reexamination Certificate

active

07099969

ABSTRACT:
A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the scaling features of the PCI Express standard. During operation of the computer system, the status of the endpoints is detected and unused links (or unused portions of links) are rerouted to other endpoints.

REFERENCES:
patent: 6665742 (2003-12-01), Owen et al.
patent: 6918001 (2005-07-01), Fanning
patent: 2005/0012747 (2005-01-01), Sauber
PCI Express Base Specification Revision 1.0a,PCI-SIG, pp. 1-15, 27-35,and 167-185, Apr. 15, 2003.
“Creating a Third Generation I/O Inerconnect” by Ajay V. Bhatt, Technology and Research Labs, Intel Corporation, White Paper, 8 pages, 2002.

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