Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-08-14
2007-08-14
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S122000, C711S154000
Reexamination Certificate
active
10956560
ABSTRACT:
In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled and to determine whether the current utilization is below a predetermined utilization value. The configuration unit may selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.
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Golden Michael L.
Klass Richard E.
Advanced Micro Devices , Inc.
Curran Stephen J.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Thai Tuan V.
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