Dynamic reconfigurable memory hierarchy

Details Dynamic reconfigurable memory hierarchy Dynamic reconfigurable memory hierarchy

2011-03-08

2011-03-08

Song, Jasmine (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S001000, C711S117000, C711S119000, C711S126000, C711S128000, C711S129000, C711S205000, C711S206000, C711S207000, C365S049100, C365S185130, C365S230030, C365S230060

Reissue Patent

active

RE042213

ABSTRACT:
A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

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Stolowitz Frod Cowger LLP; Related Case Listing Sheet, Apr. 9, 2010, 1 page.
Balasubramonian et al.; Dynamic Memory Hierarchy Performance Optimization; International Symposium on Computer Architecture; Jul. 11, 2000.

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