Dynamic read-write random access memory

Details Dynamic read-write random access memory Dynamic read-write random access memory

1988-01-11

1988-12-27

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365149, 365203, 365210, 365226, G11C 1124

Patent

active

047945710

ABSTRACT:
A dynamic read-write random access memory (DRAM) including a memory cell, a word line and a bit line. The memory cell has a capacitor and a MOS transistor which has a gate connected to the word line, a drain terminal connected to the capacitor and a source terminal connected to the bit line. The DRAM further includes a supply circuit for applying to the bit line a voltage level having a value between the voltage level of the word line and the voltage level of the drain terminal of the MOS transistor when the memory cell is not selected, so as to prevent leakage current from flowing through the MOS transistor.

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patent: 4368529 (1983-01-01), Furuyama et al.
"A 5V-Only 64K Dynamic RAM", Lionel S. White, Jr. et al., 1980 ISSCC Dig. Tech. Papers, pp. 230-231, Feb. 1980.
"A 256K RAM Fabricated with Molybdenum-Polysilicon Technology", T. Mano et al., 1980 ISSCC Dig. Tech. Papers, pp. 234-235, Feb. 1980.
Patent Abstracts of Japan, vol. 6, No. 75 (P-114) [953], 5-12-82; & JP A-57-12-483 (Nippon Denki K.K.) 1-22-82.
"Analog Capabilities on Metal Gate CMOS Arrays"-8080 Wescon Technical Papers; vol. 26, Sep. 1982, pp. 1-6.

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