Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1989-06-12
1991-01-08
Bowler, Alyssa H.
Static information storage and retrieval
Read/write circuit
Data refresh
36523006, 365233, G11C 700, G11C 11406, G11C 11401
Patent
active
049842080
ABSTRACT:
A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.
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Patent Abstracts of Japan, vol. 5, No. 48 (P-55)[720], Apr. 7, 1981 for JP-A-56 3496 (Hitachi Seisakusho K.K.) 14-01-81.
Nogami Kazutaka
Sakurai Takayasu
Sawada Kazuhiro
Bowler Alyssa H.
Kabushiki Kaisha Toshiba
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