Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent
1993-11-30
1996-04-09
Clawson, Jr., Joseph E.
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
365149, 365171, G11C 700
Patent
active
055068049
ABSTRACT:
A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
REFERENCES:
patent: 4777625 (1988-10-01), Sakui et al.
patent: 4961170 (1990-10-01), Fujitsu et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5150325 (1992-09-01), Yanigisawa et al.
Nikkei Electronics, Mar. 10, 1986 (No. 390), pp. 199-217.
Ishii Kyoko
Kinoshita Yoshitaka
Kitsukawa Goro
Kobayashi Yutaka
Matsumoto Tetsurou
Clawson Jr. Joseph E.
Hitachi , Ltd.
VLSI Engineering Corp.
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