Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-09-12
1996-12-31
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
365205, 365207, 36523006, G11C 700, G11C 800
Patent
active
055900801
ABSTRACT:
A dynamic semiconductor memory device comprises a memory array by which memory-cell units having a plurality of dynamic type memory cells connected in series are arranged in a matrix. Sense-amplifier circuits compare and amplify potential difference of a pair of data lines connected to the memory-cell units. Sense amplifier drivers charge or discharge the data lines. The memory further comprises means for changing drive capacity of the sense amplifier driver during reading-out and either restoring or writing. For example, by making the restoring or writing drive capacity smaller than the reading drive capacity, electric charge or discharge peak currents of the data lines line can be reduced.
REFERENCES:
patent: 4739500 (1988-04-01), Miyamoto et al.
patent: 5424990 (1995-06-01), Ohsawa
Hasegawa et al., "WP3.3: An Experimental DRAM with a NAND-Structured Cell", IEEE International Solid-State Circuits Conference, Session 3, pp. 46-47, 1993.
Kimura et al., "A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture", IEEE International Solid-State Circuits Conference, Session 6, pp. 106-107, 297, 1991.
Hasagawa Takehiro
Oowaki Yukihito
Kabushiki Kaisha Toshiba
Nelms David C.
Phan Trong
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