Dynamic random access memory with slanted active regions

Details Dynamic random access memory with slanted active regions Dynamic random access memory with slanted active regions

1999-11-15

2001-10-16

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000, C257S907000

Reexamination Certificate

active

06303955

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a layout structure of dynamic random access memory, more specifically, to a layout structure of dynamic random access memory with slanted active regions.
BACKGROUND OF THE INVENTION
According to the fabrication of semiconductor devices or integrated circuits, dynamic random access memory (DRAM) is an important microelectronic device and it is a storage device for storing information. Typically, a DRAM cell consists of a capacitor and a comparator. The capacitor in a DRAM cell stores electrostatic charge and the comparator in the DRAM compares the voltage level in the capacitor with a standard voltage level to determine that the voltage level in the capacitor is high level or low level. In other words, the capacitor has a high-level charge storage, the data recorded in the capacitor is indicated as “1”. Similarly, the capacitor has a low-level charge storage, the data recorded in the capacitor is indicated as “0”.
The capacitor of a DRAM cell is fabricated on the drain region of the cell and the capacitor electrically connects to the active region of the cell by using a contact plug between the capacitor and the active region. The active region electrically connects to the bit lines of the DRAM cell by using a contact window. Consequently, the manufacture of a DRAM cell must use two etching masks, one etching mask is adapted for defining the electrical contact region of the capacitor region in order to align the capacitor region with the drain region of the cell, another etching mask is adapted for defining the capacitor node of a crown-type bottom electrode.
Referring to
FIG. 6
, a layout structure of a DRAM cell is shown. A DRAM has several active regions
400
that are formed on the semiconductor substrate and the active regions
400
have a square shape. Several word line regions
500
are formed on the substrate for controlling the transistors of the DRAM. Additionally, several bit line regions
100
are formed on the substrate and each of the bit line regions is protected by spacers
110
for insulating isolation. Besides, the spacers are formed from silicon nitride material. The bit line contact holes
200
are formed in interlayer dielectric layers of the DRAM and the contact holes
200
cross the bit line regions
100
and the active regions
400
for electrical coupling between the bit line regions
100
and the active regions
400
.
The bit line contact holes
200
are formed on the active regions
400
and the bit line regions then refill to cover on/in the bit line contact holes
200
for electrical coupling. Nevertheless, the bit line contact holes
200
are partially covers on the active regions
400
and the bit line regions
100
are partially on the bit line contact holes
200
. Thus, the bit line contact holes
200
between the bit line regions
100
and the active regions
400
is hard to be completely covered. Furthermore, the substrate between the bit line regions
100
is indicated as a capacitor regions
300
, in other words, the capacitors of the DRAM are formed on the active regions
400
between the bit line regions
100
for connecting the drain regions of the DRAM. During the etching process of the capacitor regions
300
, there is no good isolation reliability around the bit line contact holes
200
and it can not make sure the isolation between the capacitors and the bit lines.
The layout structure of the DRAM depicted in
FIG. 6
includes two electrical contacts, the first electrical contact is located between the bit line regions and the active regions, the second electrical contact is located between the capacitors and the active regions of the DRAM. The first electrical contact is located at the contact hole regions of the bit lines and it is formed by using lithography process and the etching process to etch interlayer dielectric layers for forming contact holes exposing the partial portion of the active regions and the bit line regions. The conductive material is refilled into the contact holes to serve as the electrical connection between the bit lines and the active regions. The second electrical contact is formed by using lithography and etching process during the formation of the capacitor and the contact holes of the drain regions formed in the interlayer dielectric layer. Consequently, as the contact hole of the drain region is precisely defined in position, the electrical contacts of the drain regions have good reliability. The manufacture of the first electrical contact is to form a bit line contact hole for the connection between the bit lines and the active region and the electrical conductive material is adapted for the connection between the bit line and the active region. In prior art, the bit line region do not fully overlaps on the active region and a bad insulating isolation exists therein.
The trend of fabricating DRAM cells is to shrink the size of the cells, that is, to decrease the planar area of the cells for increasing the device integration on silicon wafers. Thus, the distance between the bit lines of DRAM is shrunken to increase the integrity of integrated circuits. As the distance between the bit lines is shrunken, the isolation reliability between the bit line regions and the contact plugs of the capacitors between the bit line regions is simultaneously degraded. At the same time, to simplify the fabrication of the DRAM is an important issue for fabricating the DRAM. Therefore, it is needed that the layout structure of the active regions and the bit line regions to improve the isolation reliability between the bit line regions and the capacitor regions, not to reduce the integrity density of the DRAM.
SUMMARY OF THE INVENTION
The present invention provides a layout structure of DRAM with slanted active regions and a method to manufacture the structure. Initially, slanted active regions are formed on a substrate and the active regions have a S-type shape. Afterwards, word line regions for controlling the transistors of DRAM are formed on the substrate. Bit line regions are formed on the substrate and cross the slanted active regions so that the first ends and the second ends of the active regions are respectively located on the first side and the second side of the bit line regions. Furthermore, there are bit line contact holes on the slanted active regions and the bit line regions fully cover on the bit line contact holes to form an electrical connection between the slanted active regions and the bit line regions. Finally, an etching process is performed on the interlayer dielectric layers between the bit line regions to form capacitor regions.
The present invention provides a structure of DRAM with slanted active regions. The bit line regions could fully cover on the bit line contact holes of the slanted active regions to prevent the bit line contact holes from the connection with the capacitor regions.
The present invention provides a layout structure of DRAM with slanted active regions. The bit line regions of DRAM cross the slanted active regions and the spacers of the bit line regions protect the bit line contact holes on the slanted active regions to prevent the bit line contact hole from being etched during the etching process of the capacitor regions of DRAM.
The present invention provides a method for fabricating DRAM with slanted active regions. Slanted active regions are defined in the semiconductor substrate and the bit line regions completely cover on the bit line contact holes on the active regions for protecting the bit line contact holes.


REFERENCES:
patent: 5149665 (1992-09-01), Lee
patent: 5298775 (1994-03-01), Ohya
patent: 5374576 (1994-12-01), Kimura et al.
patent: 5612241 (1997-03-01), Arima
patent: 5747844 (1998-05-01), Aoki et al.
patent: 6074908 (2000-06-01), Huang
patent: 6077738 (2000-06-01), Lee et al.
patent: 6127260 (2000-10-01), Huang

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