Dynamic random access memory with low-power refresh

Details Dynamic random access memory with low-power refresh Dynamic random access memory with low-power refresh

2007-12-20

2010-06-22

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S201000, C365S185080, C365S189070, C365S230090

Reexamination Certificate

active

07742355

ABSTRACT:
A technique to reduce refresh power in a DRAM. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Testing the DRAM uses a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory.

REFERENCES:
patent: 6778457 (2004-08-01), Burgan
patent: 7116602 (2006-10-01), Klein

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