Dynamic random access memory with isolated well structure

Details Dynamic random access memory with isolated well structure Dynamic random access memory with isolated well structure

1995-06-29

1997-09-23

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257369, 365182, H01L 2702

Patent

active

RE0356131

ABSTRACT:
A semiconductor memory device includes a first conductivity type well in a first conductivity type semiconductor substrate surrounded by a second conductivity type well, one of a memory cell and an external input circuit arranged on the first conductivity type well and the other disposed outside the second conductivity type well. A predetermined power supply voltage is applied to the second conductivity type well and the first conductivity type well is connected to ground. In the structure, charge carriers injected from the external input circuit are absorbed in the second conductivity type well. As a result, the charge carriers are prevented from reaching the memory cell and destroying data stored therein. Therefore, it is possible to miniaturize transistors and increase integration density of dynamic random access memory devices without degrading the source to drain dielectric strength.

REFERENCES:
patent: 4163245 (1979-07-01), Kinoshita
patent: 5079613 (1992-01-01), Sawada et al.
patent: 5404042 (1995-04-01), Okumura et al.
Fujii et al., "A 45-ns 16-Mbit DRAM With Triple-Well Structure", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1170-1175.
1989 ISSCC Digest of Technical Papers, IEEE International Solid-State Circuit Conference, Feb. 1989, pp. 248-249.

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