Dynamic random-access memory with high-speed word-line driver ci

Details Dynamic random-access memory with high-speed word-line driver ci Dynamic random-access memory with high-speed word-line driver ci

1997-06-20

1999-01-26

Cunningham, Terry D.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365203, G11C 704

Patent

active

058645080

ABSTRACT:
A random-access memory includes an array of rows and columns of memory cells. Word lines are associated with rows of memory cells, bit lines lines are with columns of memory cells. A row decoder and a core control circuit are connected to the word lines. A column decoder and a sense amplifier circuit are connected to the bit lines. An individual cell may be addressed by addressing an individual column through a column decoder controlling the voltage on each word line, and through a row decoder controlling the voltage on each word line in response to specified row and column addresses input via row and column address buffers. A booster circuit provides the row decoder with a boosted voltage as a word-line drive voltage. This voltage has been transmitted to a pre-decoder section in the core control circuit before the row address is acquired in the row decoder.

REFERENCES:
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IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1128-1132, M. Horiguchi, et al., "Dual-Operating-Voltage Scheme For A Single 5-V 16-MBIT Dram".
Kitsukawa, et al. "A 1-Mbit BiCMOS Dram Using Temperature-Compensation Circuit Techniques", Jun. 1989, pp. 597-602.
Nakagome, et al. "A 1.5V Circuit Technology for 64Mb Drams", 1990, pp. 17, 18.

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