Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-08-26
1997-12-09
Wallace, Valencia Martin
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257296, 257301, 257303, 257306, 257308, 257309, 437 52, 437 60, 437919, H01L 27108, H01L 2976, H01L 2994, H01L 2170
Patent
active
056963955
ABSTRACT:
A method is described for fabricating a dynamic random access memory having a high capacitance fin-type stacked capacitor. The method begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. Source/drain structures are formed within the device areas of said semiconductor substrate associated with the gate structures. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The fin-type stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas. Alternating layers of polysilicon and insulator are deposited over the device and field oxide areas with a first polysilicon layer being contact to the device areas for electrical contact and the last polysilicon layer being the topmost of the alternating layers. The stack of alternating polysilicon and insulator layers are now patterned to form the basis of the stacked capacitors. The exposed edges of the insulator layers are controlably and laterally isotropic etched to increase the planned surface area of the capacitor by forming fin-type structures. A fourth polysilicon layer is deposited over the device and field oxide areas to complete the lower electrode of the stacked capacitor. A capacitor dielectric layer is formed over the lower electrode of the stacked capacitor and the top polysilicon electrode layer is deposited thereover to complete the stacked capacitors.
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T. Ema, et al. "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMs" IEDM 1988 pp. 592-595.
Ackerman Stephen B.
Industrial Technology Research Institute
Martin Wallace Valencia
Saile George O.
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