Dynamic random access memory with FET equalization of bit lines

Static information storage and retrieval – Read/write circuit – Including signal clamping

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365203, 365222, 365233, 365206, G11C 700, G11C 1140

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active

050539973

ABSTRACT:
A dynamic random access memory with a folded bit line structure (BLL.sub.j1, BLL.sub.j1, BLR.sub.j1 BLR.sub.j1), each pair of bit lines being divided into a plurality of blocks (MCB.sub.j1, MCB.sub.j2), comprises equalizing transistors (Q.sub.j9, Q.sub.j10) each of which is provided for each pair of divided bit lines to equalize the pair of divided bit lines. The equalizing transistors (Q.sub.j9, Q.sub.j10) stop equalizing selectively and at different times among the blocks.

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L. Arzubi, "Bit Line Cascading in Semiconductor Storage Chips", IBM Technical Disclosure Bulletin, vol. 22, No. 8B, Jan. 1980.
ISCC Digest of Technical Papers 1984, pp. 279-279 of Roger I. Kung et al.

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