Static information storage and retrieval – Read/write circuit – Including signal clamping
Patent
1987-12-08
1991-10-01
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Including signal clamping
365203, 365222, 365233, 365206, G11C 700, G11C 1140
Patent
active
050539973
ABSTRACT:
A dynamic random access memory with a folded bit line structure (BLL.sub.j1, BLL.sub.j1, BLR.sub.j1 BLR.sub.j1), each pair of bit lines being divided into a plurality of blocks (MCB.sub.j1, MCB.sub.j2), comprises equalizing transistors (Q.sub.j9, Q.sub.j10) each of which is provided for each pair of divided bit lines to equalize the pair of divided bit lines. The equalizing transistors (Q.sub.j9, Q.sub.j10) stop equalizing selectively and at different times among the blocks.
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ISCC Digest of Technical Papers 1984, pp. 279-279 of Roger I. Kung et al.
Miyamato Hiroshi
Yamada Michihiro
Bowler Alyssa H.
Hecker Stuart N.
Mitsubishi Denki & Kabushiki Kaisha
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