Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-12-01
2002-11-12
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S207000, C365S230080
Reexamination Certificate
active
06480433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the design to test properties of DRAM circuits and particularly to underlying DRAM's in optical spatial light modulators.
2. Description of the Related Art
An important characteristic of any memory circuit is its ability to be automatically tested at the chip level. A typical DRAM cell
100
, comprised of a NMOS transistor
101
and a storage capacitor
102
, is shown in FIG.
1
. Such memory cells are arranged in a matrix made up of rows and columns, where the columns are connected together and the rows are connected together. A wordline signal is used to address the various rows in the array while a bitline is used to address the columns. In testing the array, the binary state of each cell is read out and observed for correctness. One of the problems encountered in testing a DRAM array where all the bitlines in a column of cells are connected together is that the inherent bitline capacitance
103
can be large relative to the cell capacitance
102
. This can result in very small cell readout differential voltages, as illustrated by the following voltage capacitance relationship:
Vdifferential_swing
=
C
1
C
2
(
V
1
-
V
2
)
where C
1
and C
2
are capacitors
102
and
103
, respectively, V
1
is the cell output voltage, and V
2
is the bitline precharge voltage, V
EE
/2, shown in FIG.
1
. As can be seen from the equation, as the bitline capacitance, C
2
, becomes large relative to the cell storage capacitance C
1
, the readout differential voltage can become quite small.
In typical DRAM circuits, the bitline capacitance problem discussed above is overcome by breaking the DRAM array
200
into several cell banks
201
-
204
(four shown), as shown in FIG.
2
. This allows the relationship between the capacitance of capacitors C
1
and C
2
to remain small enough that adequate cell readout voltages are obtainable.
However, the DRAM cells used as the underlying memory structure in large area spatial light modulators, such as digital micromirror devices (DMD), as shown in
FIG. 3
, are not necessarily conducive to being broken into banks since the mirrors are typically all connected together. In these large area arrays the large bitline capacitance can completely override the cell voltage during the readout test mode making it extremely difficult to test the memory array with conventional methods. As a result, an innovative method is needed for 100% testing the DRAM cells in these large area arrays. This invention solves this testing problem with an effective differential readout method and circuit for automatically testing the large area DRAM memory cells in these devices.
SUMMARY OF THE INVENTION
This invention discloses a differential amplifier circuit used to test underlying DRAM memory cells in large area spatial light modulator arrays by significantly increasing the cell capacitance to bitline capacitance ratio for the devices. Since these large area optical arrays can't be sub-divided into smaller banks for testing, as in the case of standard DRAM memory chips, the large bitline capacitance overrides the cell capacitance to the extent that it's difficult to readout the cell voltage. This invention overcomes the problem created by the large bitline capacitance.
The differential amplifier circuit of this invention compares each bitline with its adjacent bitline on a cell-to-cell basis. By loading a checkerboard pattern, reading out the results, loading an inverse checkerboard pattern, and reading out again, 100% test coverage of the array is accomplished. In this manner, the differential voltage readout is effectively doubled, to:
Vreadout
=
&LeftBracketingBar;
2
C
1
C
2
(
V
1
-
V
2
)
&RightBracketingBar;
In this case, the true data is not read, as in a conventional DRAM, but rather the differential voltage of a cell compared with it's adjacent cell is readout. This technique provides an effective DRAM test procedure which is independent of bitline capacitance.
REFERENCES:
patent: 5796671 (1998-08-01), Wahlstrom
patent: 6185119 (2001-02-01), Haeberli et al.
patent: 6335896 (2002-01-01), Wahlstrom
Auduong Gene N.
Brady III Wade James
Brill Charles A.
Hoang Huan
Telecky , Jr. Frederick J.
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