Dynamic random access memory with complementary bit lines and ca

Details Dynamic random access memory with complementary bit lines and ca Dynamic random access memory with complementary bit lines and ca

1992-12-03

1994-11-22

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Capacitors

365196, 365203, G11C 1124

Patent

active

053674812

ABSTRACT:
A DRAM comprising a memory cell array having a dynamic type memory cell having one MOS transistor for transfer gate and one capacitor for data storage with one end connected to the transistor, a word line connected in common to the gate of each transistor in each row of the memory cell array, a bit line connected in common to each transistor in each column of the memory cell array, a bit line precharge circuit provided so as to precharge the bit line of the memory cell array at a predetermined timing, a capacitor common line provided so as to correspond to a pair of complementary bit lines of the memory cell array and connected in common to the other end of the capacitor of the memory cell, a capacitor common precharge circuit provided so as to precharge the capacitor common line at predetermined timing, capacitor common line transfer gates for connecting the capacitor common line to the input nodes of a sense amplifier and on/off controlled at a predetermined timing, and bit line transfer gates for connecting the input nodes of the sense amplifier and the complementary pair of bit lines, respectively, and on/off controlled at a predetermined timing.

REFERENCES:
patent: 4598387 (1986-07-01), Chuang et al.
patent: 4792922 (1988-12-01), Mimoto et al.
patent: 4943944 (1990-07-01), Sakui et al.
patent: 5051954 (1991-09-01), Toda et al.
Asakura, M. et al, "Cell-Plate Line Connecting Complementary Bitline (C3) Architecture for Battery Operating DRAMs", pp. 59-60, dated May 30, 1991.

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