Dynamic random access memory with a simple test arrangement

Details Dynamic random access memory with a simple test arrangement Dynamic random access memory with a simple test arrangement

1995-09-28

1996-09-24

Nelms, David C.

Static information storage and retrieval

Read/write circuit

365201, 365203, 371 213, G11C 700, G11C 2900

Patent

active

055597394

ABSTRACT:
A Dynamic Random Access Memory (DRAM) including an array of memory cells arranged in rows and columns, a word line in each row responsive to a row address and, a pair of complementary bit lines in each column. The DRAM also includes a sense amp in each column connected between a sense enable and the pair of complementary bit lines. The sense amp is a pair of cross coupled NFETs, with the sources of the NFETs connected to the sense amp enable. A bit line pre-charge is connected to each pair of complementary bit lines. The bit line pre-charge is connected between the complementary bit line pair and a reference voltage. A test control circuit selectively holds the sense amp disabled and the bit line pairs in a pre-charge state in response to a test control signal. An active sense amp load connected between the sense amp and a load enable latches data in the sense amp. The active sense amp load is a pair of cross coupled PFETs connected to the sense amp with the sources of the PFETs connected to the load enable. Optionally, each column may include a plurality of bit line pairs, each pair connected to a mux input. In this embodiment, the sense amp is connected between the mux's output and the sense amp enable. Because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, the voltage stored in the cells is varied. So, cell signal margin is tested by varying cell signal V.sub.S. V.sub.S may be selected to determine both a high and a low signal margin.

REFERENCES:
patent: 4839865 (1989-06-01), Sato et al.
patent: 5153853 (1992-10-01), Eby et al.
patent: 5157629 (1992-10-01), Sato et al.
patent: 5187685 (1993-02-01), Sato et al.
patent: 5265056 (1993-11-01), Butler et al.
patent: 5305266 (1994-04-01), Roundtree
patent: 5515326 (1996-05-01), Hirose et al.
K. S. Gray, et al, "Sense Amplifier Signal Margin Circuit" IBM Technical Disclosure Bulletin, V. 22, No. 1, pp. 56-57, Jun. 1979.
D. G. Morency, et al, "Bit Line Offset Circuit" IBM Technical Disclosure Bulletin, V. 27, No. 7B, pp. 4126-4127, Dec. 1984.
"Signal Margin Test for 4-D, 4-D with Poly Load or 6-D Random-Access Memories" IBM Technical Diclosure Bulletin, V. 28, No. 11, pp. 4792-4793, Apr. 1986.

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