Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1988-07-27
1990-06-19
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Data refresh
365201, 371 381, G11C 700
Patent
active
049359002
ABSTRACT:
A dynamic random access memory includes a self-refreshing function, in which an error correction device for detecting and correcting an error in the data of the memory cell during the refreshing operation of the memory cell data is provided. The clock period of a control clock generator for controlling the refreshing and error correcting operation is made variable. Specifically, the clock period of the clock generator is maintained in the vicinity of a maximum acceptable value dependant on the pause time of the memory cell in response to an error detection signal generated at the time of error correction by the error correction device. According to this configuration, if the phase time of the memory cell is changed significantly due to the manufacturing process condition the refreshing operation can be effected at a period near the maximum acceptable value, so that the self-refreshing current consumption may be decreased. Furthermore, if the phase time varies depending on the change in the operating condition or characteristic changes due to the time passage, the clock period values in response to such change, so that it is possible to operate in the maximum self-refreshing period depending on the conditions, without-resulting in a malfunction in the refreshing operation.
REFERENCES:
patent: 4333167 (1982-06-01), McElroy
patent: 4412314 (1983-10-01), Proebsting
patent: 4644184 (1987-02-01), Miyawaki et al.
patent: 4682306 (1987-07-01), Sakurai et al.
patent: 4694454 (1987-09-01), Matsuura
patent: 4748627 (1988-05-01), Ohsawa
patent: 4758992 (1988-07-01), Taguchi
Matsushita Electronics Corporation
Popek Joseph A.
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