Dynamic random access memory with a normal precharge mode and a

Details Dynamic random access memory with a normal precharge mode and a Dynamic random access memory with a normal precharge mode and a

1998-06-01

1999-07-06

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711158, 711169, 365193, 365203, G06F 1200, G11C 700

Patent

active

059208856

ABSTRACT:
A dynamic random access memory (DRAM) includes priority access control circuitry, where the DRAM has a first precharge mode and a priority precharge mode. In the first precharge mode, the array is precharged during an external row address strobe (RAS) and accessed during an active state of the external RAS. In the priority precharge mode, the array is precharged during a precharge state of an internal RAS initiated by a priority signal received during any one of the precharge and active states of the external RAS, where the priority access control circuitry returns to the first mode on a subsequent precharge state of the external RAS.

REFERENCES:
patent: 5555526 (1996-09-01), Kim
patent: 5600605 (1997-02-01), Schaefer
patent: 5623453 (1997-04-01), Shinozaki

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